Variable Capacitance Element With Buffer Layer For Tunable Filter
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Solution Overview
Problem
Existing variable capacitance elements with dielectric layers of barium strontium titanate (BST) cannot be effectively formed on piezoelectric substrates due to high deposition temperatures, leading to degraded piezoelectric characteristics, warping, and peeling issues, which hinders the miniaturization of piezoelectric devices and results in insufficient filter characteristics.
Innovation Solution
A variable capacitance element is created with a dielectric layer whose relative dielectric constant varies with applied voltage, using a buffer layer with specific crystal orientations and materials like Pt(111) or Pt(200) on a piezoelectric substrate, allowing for the deposition of BST and reducing dielectric loss, thereby enhancing capacitance variation and filter characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a barium strontium titanate (BST) dielectric layer is formed on a piezoelectric substrate to achieve small-sized element with large capacitance variation, then capacitance variation is improved, but the piezoelectric substrate experiences warping, breaking, and BST film peeling due to high deposition temperature (800-900°C)
Solution Approach 1:
An orientation control layer is introduced as an intermediary between the piezoelectric substrate and the BST dielectric layer. This layer mediates the thermal stress and deposition process, allowing BST to be formed at reduced temperatures without direct contact with the substrate, thereby preventing warping, breaking, and peeling while maintaining capacitance variation performance
Solution Approach 2:
The deposition temperature parameter is changed from the conventional high range (800-900°C) to a lower range (400-700°C) by using the orientation control layer approach. This parameter change enables BST film formation that maintains good characteristics while preventing substrate damage and film peeling
2Manufacturing precision
If BST dielectric layer is deposited at high temperature (800-900°C) to achieve good dielectric characteristics, then dielectric performance is improved, but piezoelectric characteristics are degraded and substrate warping or breaking occurs
Solution Approach 1:
The orientation control layer serves as a protective intermediary that decouples the deposition process from the piezoelectric substrate. It allows the BST layer to be deposited at lower temperatures while maintaining good dielectric characteristics, preventing the degradation of piezoelectric properties that would occur at high temperatures
Solution Approach 2:
The deposition temperature is reduced from 800-900°C to 400-700°C through the use of the orientation control layer. This parameter change enables the formation of BST with good dielectric characteristics while preserving the piezoelectric characteristics of the substrate
3Ease of manufacture
If conventional variable capacitance element structure is used with separate insulator layer and electrode layers, then ease of manufacture is maintained, but device size and thickness are increased
Solution Approach 1:
The orientation control layer is designed to serve multiple functions simultaneously: it controls crystal orientation for BST deposition, acts as a barrier layer, and functions as part of the electrode structure. This merging of functions reduces the total number of separate layers needed, thereby reducing element size and thickness while maintaining manufacturing simplicity
Solution Approach 2:
The orientation control layer is a multi-functional element that performs orientation control, thermal stress management, and electrical function. This multi-functionality allows the elimination of separate insulator and electrode layers in certain configurations, reducing overall device size without complicating the manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a small, thin, and efficient tunable filter with reduced interconnect resistance and parasitic components, achieving significant improvements in filter characteristics and capacitance variation while maintaining good piezoelectric device performance.
Implementation Method 1
a dielectric layer whose relative dielectric constant varies in accordance with an applied voltage
Implementation Method 2
a buffer layer with specific crystal orientations and materials like Pt(111) or Pt(200) on a piezoelectric substrate, allowing for the deposition of BST
Data Source
AI summary
A variable capacitance element includes a piezoelectric substrate, a buffer layer located on the piezoelectric substrate with an orientation, a dielectric layer located on the buffer layer and having a relative dielectric constant that varies in accordance with an applied voltage, and a first electrode and a second electrode arranged to apply an electric field to the dielectric layer.