Variable Capacitance Circuit Parasitic Diode Suppression
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Solution Overview
Problem
Existing variable capacitance circuits using MOS-FETs suffer from signal distortion due to parasitic diodes, which are activated by input signals, leading to capacitance variations and nonlinearity, and require high bias voltages and large resistors, making integration challenging.
Innovation Solution
A variable capacitance circuit design where a plurality of series circuits of capacitors and MOS-FET paths are connected in parallel, with pull-up resistors and inverters, allowing capacitance control via digital data, suppressing signal distortion and reducing current consumption without high bias voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a parasitic diode is present in the FET structure, then the circuit can be integrated, but signal distortion occurs when the input signal amplitude exceeds 0.5Vp
Solution Approach 1:
The patent applies preliminary anti-action by pre-biasing the parasitic diode through a DC voltage applied to the back gate of the FET. This DC bias is established before the input signal arrives, creating a reverse bias condition that prevents the parasitic diode from turning on during signal operation. The bias voltage counteracts the forward bias that would normally occur when the input signal exceeds 0.5Vp, thereby preventing signal rectification and distortion while maintaining the integrated FET structure.
2Object-affected harmful factors
If a high bias voltage is applied to suppress parasitic diode effects, then signal distortion is reduced, but current consumption increases
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the back gate voltage of the FET to optimize the bias condition of the parasitic diode. Instead of using a fixed high bias voltage that would cause excessive current consumption, the back gate voltage is controlled to vary with the operating conditions, maintaining just enough reverse bias to prevent parasitic diode conduction during signal operation. This dynamic parameter adjustment reduces unnecessary current flow while still suppressing signal distortion.
3Adaptability or versatility
If the FET is turned off to control capacitance, then variable capacitance is achieved, but the parasitic diode becomes active and causes nonlinearity
Solution Approach 1:
The patent introduces an intermediary element - the back gate voltage - that mediates between the need for capacitance variability and the requirement for linear operation. By controlling the back gate voltage, the parasitic diode is kept in a reverse-biased state even when the FET is turned off for capacitance control. This intermediary voltage control allows the main channel to be switched off for capacitance modulation while the parasitic diode remains inactive, preventing nonlinearity and maintaining signal integrity throughout the capacitance variation range.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively varies capacitance with digital data, suppresses signal distortion, and is suitable for integration with low current consumption and reduced parasitic diode effects, enhancing the circuit's performance and integration capabilities.
Implementation Method 1
the parasitic diode DPR is turned on and the input signal is rectified by the parasitic diode DPR
Implementation Method 2
the junction capacitance of the parasitic diode DPR is varied by the applied signal voltage
Data Source
AI summary
A switch circuit which can operate with a single low voltage is provided. A plurality of (i=0 to n) series circuits of a capacitor (Ci) and a path of the drain-source of a MOS-FET (Qi) are connected in parallel to each other between a first terminal T1 and a second terminal T0. In each of the series circuits, a pull-up resistor Ri is connected between an output terminal of an inverter Ai and a junction between the capacitor Ci and the MOS-FET (Qi). Each bit bi of digital data for controlling the capacitance is supplied to the gate of the MOS-FET (Qi) and the inverter Ai in each of the series circuits. Capacitance which varies in response to the value of the digital data is obtained between the first terminal T1 and the second terminal T0.