Variable Capacitance Negative Voltage Generator for Memory Write Speed

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Solution Overview

Problem

Semiconductor memory devices face challenges in maintaining efficient write operations as power supply voltage decreases, leading to increased write times or data retention failures due to insufficient voltage levels across memory banks with different numbers of rows.

Innovation Solution

A negative voltage generator with a variable capacitance unit and switching mechanism that selects appropriate coupling capacitors based on parasitic capacitance, ensuring a consistent negative voltage level across memory banks, complemented by a high voltage applying unit to facilitate accurate data writing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If power supply voltage is decreased to reduce power consumption, then energy efficiency is improved, but write operation speed and data retention reliability deteriorate

Engineering Contradiction:

Improvepower consumptionVSAvoidwrite operation speed

Core Design Contradiction:

Use of energy by moving objectVSProductivity

Solution Approach 1:

The patent applies parameter changes by dynamically adjusting the capacitance value of the coupling capacitor based on the memory bank's row count. By selecting different capacitance values (first capacitance for first number of rows, second capacitance for second number of rows), the system compensates for voltage drops during write operations, enabling maintainment of write speed and data retention even at reduced power supply voltages.

Inventive Principle:

Principle #35Parameter changes

2Use of energy by moving object

If power supply voltage is decreased to reduce power consumption, then energy efficiency is improved, but data retention reliability deteriorates

Engineering Contradiction:

Improvepower consumptionVSAvoiddata retention

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The patent uses parameter changes by adjusting the coupling capacitor's capacitance value according to the specific memory bank configuration. This dynamic parameter adjustment ensures that sufficient negative voltage is generated during write operations to overcome leakage currents and maintain data retention reliability, even when the overall power supply voltage is reduced for energy efficiency.

Inventive Principle:

Principle #35Parameter changes

3Manufacturing precision

If different negative voltage levels are provided to memory banks with different row counts, then voltage matching is improved, but device complexity increases

Engineering Contradiction:

Improvevoltage level matchingVSAvoidcapacitance selection mechanism

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the capacitance selection into discrete, predefined options (first coupling capacitor for first number of rows, second coupling capacitor for second number of rows). This segmented approach allows precise voltage matching for different memory bank configurations while keeping the selection mechanism simple and manageable through bank select signals.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements parameter changes by switching between different capacitance values based on the memory bank's row count. The bank select signal triggers the appropriate capacitance value selection, enabling precise control of negative voltage levels for each memory bank type without requiring complex continuous adjustment mechanisms.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables rapid and correct write operations across memory banks with varying row counts by maintaining consistent voltage levels, even at reduced power supply voltages, thereby improving data retention and reducing circuit complexity.

Implementation Method 1

a variable capacitance unit having a plurality of capacitance states. The negative voltage generator may included a plurality of discrete capacitors connected through switches in parallel to a pair of nodes

Methodology Applied

Scientific EffectCapacitance: Capacitance

Implementation Method 2

The stored negative voltage charge is then divided between the variable capacitance unit and the parasitic capacitance of the global bitline pair and the parasitic capacitance of the first local bitline pair

Methodology Applied

Scientific EffectParasitic capacitance: Parasitic Capacitance

Data Source

PatentUS8934313B2Negative voltage generator and semiconductor memory device

Publication Date: 2015.01.13 SAMSUNG ELECTRONICS CO LTD

AI summary

A negative voltage generator includes a variable-capacitance negative voltage generating unit, a switching unit and a positive voltage applying unit. The negative voltage generating unit includes a plurality of coupling capacitors for varying the capacitance in which the negative voltage is charged. The negative voltage generating unit selects at least one coupling capacitor of the plurality of coupling capacitors according to the number of rows (size) of a memory bank to which data is written, and charges the at least one selected coupling capacitor to a negative voltage. The switching unit selects one bitline of a bitline pair having complementary first and second bitlines in response to the data, and connects the at least one selected coupling capacitor to the selected bitline. The positive voltage applying unit applies a positive (high) voltage to an other bitline of the bitline pair.