Variable Capacitor for Non-Volatile Memory Booster Circuit
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Solution Overview
Problem
The existing nonvolatile semiconductor memory devices face reduced performance due to varying capacitance between word lines, which affects the boosting time of the booster circuit, leading to inefficient operation during writing, reading, and erasing operations.
Innovation Solution
The nonvolatile semiconductor memory device incorporates a capacitor with alternately arranged conductive layers that are controlled by a control circuit to adjust capacitance based on the voltages applied to memory transistors, ensuring consistent boosting time by adapting to changes in word line capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional capacitor with fixed capacitance is used in the booster circuit, then the device structure is simple, but the boosting time varies due to changing word line capacitance, reducing operation efficiency
Solution Approach 1:
The patent applies the dynamics principle by transforming the capacitor from a fixed capacitance component to a variable capacitance component. The capacitor's capacitance value is dynamically adjusted based on the operating state (reading, writing, or erasing) to match the varying word line capacitance requirements. This is achieved through a multi-plate capacitor structure where conductive plates can be selectively connected to different potentials, effectively changing the active capacitance value in real-time to maintain optimal boosting performance across different operations.
Solution Approach 2:
The patent implements parameter changes by modifying the capacitance parameter of the capacitor according to different operational states. During reading operations, a smaller capacitance value is used, while during writing and erasing operations, a larger capacitance value is employed. This parameter adjustment is achieved by selectively connecting different conductive plates to ground or power potentials, thereby changing the effective capacitance seen by the booster circuit to optimize charging/discharging speeds for each operation type.
2Speed
If the capacitance of the capacitor is increased to reduce boosting time, then the boosting speed improves, but the occupied area of the capacitor increases
Solution Approach 1:
The patent applies segmentation by dividing the capacitor into multiple conductive plates (first conductive plate, second conductive plate, third conductive plate, etc.) separated by insulating layers. Instead of using a single large capacitor, the structure segments the capacitance into multiple smaller units that can be selectively activated. This allows the effective capacitance to be adjusted by connecting specific plates, achieving high capacitance when needed for fast boosting while maintaining a compact physical footprint through the layered configuration.
Solution Approach 2:
The patent transitions from a two-dimensional planar capacitor layout to a three-dimensional stacked structure with multiple conductive plates arranged vertically. This dimensional change allows the capacitor to achieve higher effective capacitance within a smaller planar area by utilizing the vertical dimension. The multi-plate configuration stacked in layers provides increased capacitance density, enabling fast boosting performance without proportionally increasing the occupied chip area.
3Area of stationary object
If a multi-plate capacitor structure is used to reduce capacitor area, then the area efficiency improves, but the device complexity increases
Solution Approach 1:
The patent merges the capacitor structure with the existing word line structure of the memory device. The conductive plates of the capacitor are formed using the same conductive layers and materials as the word lines, and the insulating layers are integrated with the existing insulation structures. This merging approach allows the multi-plate capacitor to be formed as part of the standard memory cell stack, reducing the need for separate capacitor fabrication processes and minimizing additional device complexity while achieving high area efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution maintains constant boosting time and improves the performance of the semiconductor memory device by dynamically adjusting the capacitance of the capacitor in response to varying operational conditions.
Implementation Method 1
the control circuit is configured to control a voltage applied to each of the plurality of first conductive layers and second conductive layers according to voltages of gates of the plurality of memory transistors, thereby changing a capacitance of the first capacitor
Data Source
AI summary
A first capacitor includes a plurality of first conductive layers and second conductive layers. The first conductive layers function as a first electrode of the first capacitor, the second conductive layers function as a second electrode of the first capacitor. The first conductive layers and the second conductive layers are arranged alternately in the direction substantially perpendicular to a semiconductor substrate. A control circuit is configured to control a voltage applied to each of first conductive layers and the second conductive layers according to voltages of gates of a plurality of memory transistors, thereby changing a capacitance of the first capacitor.