Variable Capacity STT-MRAM for Power-Speed Trade-off
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Solution Overview
Problem
Conventional MRAMs face a trade-off between memory capacity and operation speed, limiting their ability to adapt to varying application requirements in processor systems, particularly in mobile devices where both power saving and high performance are necessary.
Innovation Solution
The development of a variable capacitance STT-MRAM that uses an advanced perpendicular magnetic tunnel junction as a memory element, allowing for selective adjustment of memory capacity and operation speed through a reconfigurable cell configuration, enabling adaptive storage control and optimal cache capacity selection based on application needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If MRAM is used as cache memory to achieve power saving, then power consumption is reduced, but operation speed becomes slow compared to SRAM
Solution Approach 1:
The patent implements a reconfigurable cell configuration that dynamically switches between different operational modes (first mode with 2n basic units and second mode with 2m basic units) based on application requirements. This allows the system to adaptively adjust between power-saving operation and high-speed operation, resolving the static trade-off between power consumption and operation speed in conventional MRAM cache memory
2Stability of the object's composition
If conventional cache memory configuration is used, then fixed performance characteristics are maintained, but adaptability to different application requirements is limited
Solution Approach 1:
The patent employs a reconfigurable cell configuration that can switch between different operational modes depending on the application. The mode selector enables the system to adapt its performance characteristics dynamically, providing both stability through fixed-mode operation and versatility through mode switching capability
Solution Approach 2:
The patent creates a universal cache memory structure that can serve multiple application types by implementing different operational modes. The same physical memory structure can be configured for different applications (e.g., mobile devices requiring power saving versus applications requiring high performance) through the reconfigurable cell architecture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables simultaneous power saving and high performance by dynamically varying cache capacity and operation speed according to application demands, optimizing both latency and memory access speed in processor systems.
Implementation Method 1
an advanced perpendicular magnetic tunnel junction as a memory element
Data Source
AI summary
According to one embodiment, a processor system includes a variable capacity memory. The memory includes a memory cell array including basic units, each of the basic units including one cell transistor and one variable resistance element, a mode selector switching between first and second modes, a read/write of one bit executed in 2n basic units (n is an integer) among the basic units in the first mode, the read/write of the one bit executed in 2m basic units (m is an integer, m≠n) among the basic units in the second mode, and a control circuit which controls the switching between the first and second modes.