Variable Charge Pump Driving for Fast PLL Locking
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Solution Overview
Problem
Conventional phase lock loops experience increased frequency jittering and extended phase lock time due to rapid frequency changes, which can lead to frequency instability and failure to lock phase and frequency.
Innovation Solution
A phase lock loop design incorporating a discriminator to dynamically adjust the driving capabilities of the charge pump's pull-up and pull-down networks based on the phase difference between the reference and feedback signals, allowing for quick phase locking while minimizing jittering by varying the current driving capability accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the driving currents of the pull-up current source and pull-down current source are increased to reduce phase lock time, then the phase lock speed is improved, but frequency jittering occurs and phase lock reliability deteriorates
Solution Approach 1:
The patent applies dynamics by making the driving capability of the charge pump variable rather than fixed. The control circuit dynamically adjusts the driving currents of the pull-up and pull-down current sources based on the phase difference magnitude: using high driving current when phase difference is large (for fast locking) and reducing current when phase difference is small (for stability), thus resolving the contradiction between fast locking and frequency jittering
Solution Approach 2:
The patent changes the parameter of driving current from a constant value to a variable value that depends on phase difference. By adjusting the current magnitude based on phase difference thresholds, the system achieves both rapid phase acquisition and stable frequency locking, eliminating the trade-off between speed and stability
2Speed
If the charge/discharge rate of the charge pump is increased to raise output voltage quickly, then the frequency response speed is improved, but the capacitor discharges too fast causing output voltage to drop excessively, leading to frequency jittering
Solution Approach 1:
The patent implements feedback by continuously monitoring the phase difference between reference and feedback signals, and using this information to control the charge pump's driving capability. The control circuit creates a closed-loop system where the charge pump's operation is adjusted based on real-time phase difference feedback, preventing excessive voltage drops and frequency jittering while maintaining fast response
Data Source
AI summary
A method for reducing phase lock time and jittering and a phase lock loop (PLL) using the same adapted for PLL including a charge pump (CP) which includes a pull-up and a pull-down networks used for controlling output voltage of the CP. The output voltage is used for controlling frequency and phase of an output signal of the PLL. The method includes: receiving a reference and a feedback signals; setting the driving capabilities of the pull-up and the pull-down networks to a first driving capability when the phase difference between the reference and the feedback signals is greater than a predetermined value; setting the driving capabilities of the pull-up and the pull-down networks to a second driving capability when the phase difference between the reference and the feedback signals is smaller than the predetermined value, wherein the first driving capability is greater than the second driving capability.