Variable Chip Packaging for Disconnecting Unused ASIC Blocks
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Solution Overview
Problem
Existing semiconductor chips with multiple functional blocks face challenges in efficiently managing power consumption and configuration flexibility, leading to unnecessary power leakage and increased costs due to the need for on-die features to switch off unused blocks.
Innovation Solution
A universal chip with variable packaging configurations allows for the decoupling of unused functional blocks from the package substrate using redistribution or bumping layers, eliminating physical power connections and eliminating the need for on-die features to switch off blocks, thereby reducing power leakage and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If on-die features are added to switch off unused functional blocks, then power consumption is reduced, but device complexity and manufacturing costs increase
Solution Approach 1:
The patent extracts the power switching function from the on-die features and relocates it to the package substrate level. By using redistribution layers and bumping structures on the package substrate to control power delivery to unused functional blocks, the chip itself remains simpler without requiring integrated switches, thereby reducing device complexity while still achieving power management goals
Solution Approach 2:
The patent introduces the package substrate as an intermediary between the power source and the functional blocks. The redistribution layers and bumping structures on the package substrate act as mediators that can selectively connect or disconnect power to different functional blocks, eliminating the need for complex on-die switching mechanisms while maintaining power control capability
2Loss of energy
If on-die features are added to switch off unused functional blocks, then power leakage is reduced, but manufacturing costs increase
Solution Approach 1:
The patent removes the power switching functionality from the chip design and places it in the packaging process. By using configurable redistribution layers and bumping patterns on the package substrate, unused functional blocks can be disconnected from power without requiring additional on-die components, thus reducing manufacturing costs while effectively preventing power leakage
Solution Approach 2:
The patent performs the power disconnection action during the packaging process before the chip is deployed. By configuring the redistribution layers and bumping structures in advance during manufacturing, the system prevents power leakage from unused blocks without requiring complex on-die features, thereby reducing both power leakage and manufacturing costs
3Adaptability or versatility
If configuration flexibility is increased through multiple switches, then adaptability improves, but device complexity and costs increase
Solution Approach 1:
The patent makes the package substrate universal by designing it with configurable redistribution layers and bumping structures that can support multiple functional blocks with different configurations. The same package substrate design can accommodate various combinations of active and inactive functional blocks, providing configuration flexibility without requiring different chip designs or additional on-die switching components
Solution Approach 2:
The patent segments the power delivery control function across multiple independent redistribution layer configurations and bumping patterns on the package substrate. Each functional block can be independently controlled through its own set of redistribution layers and bumps, allowing flexible configuration of different functional block combinations without requiring complex inter-block switching mechanisms on the chip
Data Source
AI summary
Apparatuses include a package substrate with package bonding pads and a die electrically coupled to the package substrate via conductive bonding elements. The die includes a first application-specific integrated circuit (ASIC) with first die input/output pads and a second ASIC with second die input/output pads. Each of the first die input/output pads is electrically coupled to at least one corresponding package bonding pad. At least one of the second die input/output pads is not electrically coupled to any package bonding pad, such that the second ASIC is left in an inoperable state.