Variable-Clock ADC Counting for CMOS Image Sensor Dynamic Range
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Solution Overview
Problem
Single slope analog to digital converters in CMOS image sensors perform linear signal conversion, leading to data omission in low luminance conditions and saturation in high luminance conditions, reducing the dynamic range and not being optimized for human visual perceptual characteristics.
Innovation Solution
An analog to digital converter that includes a clock control unit supplying clock signals with varying frequencies based on luminance levels, allowing for dynamic adjustment of counting rates to match human visual sensitivity, thereby optimizing signal conversion for low and high luminance conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If linear signal conversion is performed in single slope ADC, then the conversion process is simple and fast, but data omission occurs in low luminance conditions and saturation in high luminance conditions, reducing dynamic range
Solution Approach 1:
The patent applies dynamics by making the counting speed variable rather than fixed. The counting unit adjusts its counting speed according to the luminance level of the pixel signal - using faster counting for low luminance signals and slower counting for high luminance signals. This dynamic adjustment allows the ADC to optimize data capture across different luminance conditions, preventing both data omission in low luminance and saturation in high luminance, thereby resolving the contradiction between conversion speed and information loss.
Solution Approach 2:
The patent changes the parameter of counting speed based on the input signal characteristics. By detecting the luminance level of the pixel signal and adjusting the counting speed accordingly, the system transforms a static conversion process into an adaptive one. This parameter change enables the ADC to maintain optimal performance across varying signal conditions, addressing the contradiction between maintaining fast conversion and preventing data loss.
2Device complexity
If linear analog to digital conversion is performed, then the conversion process is straightforward, but it does not match human visual perceptual characteristics, reducing image quality
Solution Approach 1:
The patent makes the conversion process dynamic by adjusting counting speed according to luminance levels, which mirrors human visual perception characteristics. Human eyes are more sensitive to changes in low luminance regions, and this dynamic counting approach allocates more precision to those regions. This resolves the contradiction by making the conversion process adapt to visual perceptual characteristics without requiring a complete redesign of the entire ADC architecture.
Solution Approach 2:
The patent applies local quality by providing different counting precision for different luminance regions. Low luminance signals receive faster counting and higher precision, while high luminance signals use slower counting with appropriate precision. This localized optimization of conversion precision matches human visual characteristics and improves overall image quality without uniformly increasing complexity across all signal levels.
Data Source
AI summary
An analog to digital converter (ADC) includes a clock control unit supplying a predetermined clock signal corresponding to luminance among a plurality of clock signals having different frequencies; and a signal conversion unit comparing a ramp signal with an inputted pixel signal to generate a comparison result signal. The ADC performs counting corresponding to the predetermined clock signal supplied by the clock control unit and stores a count value counted at a time of the generating of the comparison result signal.