Variable Clock Rate Frame Transfer for Power Reduction
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Solution Overview
Problem
Current graphics processing systems face inefficiencies in power consumption and data transfer when handling graphics data, particularly in transferring frames from graphics processors to display panels, due to fixed pipelines and limited optimization techniques.
Innovation Solution
Implementing techniques such as varying clock rates, bulk frame transfer, and foveated rendering to reduce power consumption, along with compressing pixel data to optimize memory bandwidth and reduce processing load in non-region of interest areas, while utilizing unified memory architectures for efficient GPU-host communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If frames are transferred continuously from graphics processor to display panel at high clock rates, then display quality and frame rate are improved, but power consumption increases
Solution Approach 1:
The patent applies dynamics by making the clock rate variable rather than fixed. The display interface dynamically adjusts the clock rate based on the number of frames to be transferred and the time available, allowing the system to operate at high speeds when needed and reduce power consumption when fewer frames need transfer.
Solution Approach 2:
The patent changes the parameter of clock rate from a constant value to a variable that can be adjusted based on system conditions. By modifying the clock rate parameter dynamically, the system optimizes the trade-off between transfer speed and power consumption.
2Manufacturing precision
If all pixel data is transferred and processed at full resolution, then display quality is improved, but power consumption and processing load increase
Solution Approach 1:
The patent applies local quality by differentiating the processing quality for different regions of the display. Regions of interest are processed at full resolution and quality, while non-region of interest areas are processed at reduced quality or skipped entirely, optimizing the balance between overall display quality and power consumption.
Solution Approach 2:
The patent implements partial action by transferring and processing only a subset of pixel data rather than all pixels. By selectively processing only the most important regions (regions of interest), the system achieves acceptable display quality with significantly reduced processing load and power consumption.
3Quantity of substance
If clock rate is increased to transfer more frames, then frame buffer capacity requirements are reduced, but power consumption increases
Solution Approach 1:
The patent uses dynamic clock rate adjustment to temporarily increase transfer speed when bulk frame transfer is needed, reducing the burden on frame buffer capacity. After the bulk transfer, the clock rate returns to normal levels, maintaining a balance between buffer requirements and power consumption over time.
Solution Approach 2:
The patent implements periodic bulk frame transfer followed by normal operation. During periodic bulk transfer intervals, the clock rate is increased to move multiple frames efficiently, reducing frame buffer capacity requirements. Between these intervals, normal clock rates are used, creating a periodic pattern that optimizes both buffer usage and power consumption.
Data Source
AI summary
A number of frames may be transferred in one frame period to a display panel followed by at least one frame period during which no frame is transferred. During this link idle time, the display panel continues to work on the transferred frames. However, the link and/or graphics processor may be powered down during this time to reduce power consumption.