Variable Code-Rate Parity Check Matrix Controller for MLC Memory
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Solution Overview
Problem
Multilevel cell (MLC) non-volatile memory devices face challenges in precise data reading due to overlapping threshold voltage distributions, leading to increased read failure rates and errors as the number of bits programmed in each memory cell increases, causing charge loss and characteristic deterioration over time.
Innovation Solution
A controller and operating method that utilize variable code-rate parity check matrices for encoding and decoding data, allowing for precise reading by storing encoded data in memory blocks with specific code-rates and using error correction codes like LDPC to correct errors and improve data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-bit data is programmed in each memory cell to increase storage capacity, then data storage density is improved, but read reliability deteriorates due to overlapping threshold voltage distributions
Solution Approach 1:
The patent segments the data storage and reading process into multiple stages by dividing k-bit data into multiple sub-word data portions. Each sub-word is read and processed separately through iterative decoding, allowing the system to handle the complexity of multi-bit cells while maintaining read reliability despite overlapping threshold voltage distributions.
Solution Approach 2:
The patent employs dynamic adaptive decoding by iteratively adjusting code rates during the decoding process. The controller dynamically changes the code rate based on the number of error bits detected in each iteration, optimizing the balancing act between correcting errors from overlapping voltage distributions and maintaining data storage density.
2Productivity
If higher code rates are used for encoding data to reduce redundancy, then storage efficiency is improved, but error correction capability deteriorates
Solution Approach 1:
The patent implements dynamic code rate adjustment during iterative decoding. The code rate is not fixed but is adaptively changed based on the error characteristics detected in each iteration, allowing the system to optimize between storage efficiency and error correction capability depending on the actual data conditions.
Solution Approach 2:
The patent performs preliminary encoding with multiple different code rates before storage. The controller encodes data using various code rates and stores the encoded data, allowing the decoding process to select the most appropriate code rate for error correction based on the actual error patterns observed during reading.
3Measurement precision
If iterative decoding with multiple code rates is performed to improve read precision, then data reading accuracy is improved, but processing time increases
Solution Approach 1:
The patent applies partial iterative decoding by performing a limited number of decoding iterations rather than exhaustive decoding. The controller stops the iterative process when a predetermined number of iterations is reached or when error correction converges, achieving sufficient reading accuracy without the full time cost of complete iterative decoding.
Solution Approach 2:
The patent dynamically adapts the decoding process by adjusting code rates and iteration counts based on the detected error patterns. This dynamic approach allows the system to achieve high reading accuracy when needed while reducing processing time when error conditions are minimal, optimizing the trade-off between precision and speed.
Data Source
AI summary
An operation method of a controller may include encoding a first data at a first code rate such that the encoded first data is decoded by a first parity check matrix included in a variable code-rate parity check matrix and encoding a second data at a second code-rate such that the encoded second data is decoded by a second parity check matrix included in a variable code-rate parity check matrix.