Variable-Conductance Transfer Gate for Memory Bit Cell Stability
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Solution Overview
Problem
Conventional memory bit cells face a trade-off between stability and performance due to the Beta and Alpha ratios between transfer gates and storage devices, which affects read and write accesses, especially in memory systems with multiple power states.
Innovation Solution
A memory device with a bit cell that includes a transfer gate configurable to multiple conductance states based on the states of word lines, allowing independent control of conductance for different access types, such as read and write accesses, to improve stability and writeability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a higher Beta ratio between transfer gate and storage device is used, then stability is improved, but writeability deteriorates
Solution Approach 1:
The transfer gate conductance is made dynamically adjustable through multiple word lines (first word line and second word line) that can independently control the gate conductance state. This allows the system to switch between high conductance for write operations and low conductance for read operations, resolving the contradiction between writeability and stability.
Solution Approach 2:
The patent changes the conductance parameter of the transfer gate based on the operation type. By controlling the word lines to adjust the transfer gate conductance, the system optimizes the Beta ratio dynamically - using higher conductance (lower effective Beta) for writes and lower conductance (higher effective Beta) for reads, thus resolving the stability-writeability tradeoff.
2Ease of operation
If a lower Beta ratio between transfer gate and storage device is used, then writeability is improved, but stability deteriorates
Solution Approach 1:
The transfer gate conductance is dynamically controlled through multiple word lines to switch between different conductance states. During write operations, the gate conductance is increased (lower effective Beta) to improve writeability, while during read operations, it is decreased (higher effective Beta) to maintain stability.
Solution Approach 2:
The conductance parameter of the transfer gate is adjusted based on the operation type by controlling the word lines. This dynamic parameter change allows the system to have low conductance (high effective Beta) for read stability and high conductance (low effective Beta) for writeability, resolving the contradiction.
3Stability of the object's composition
If a higher Alpha ratio between transfer gate and storage device is used, then stability is improved, but writeability deteriorates
Solution Approach 1:
The transfer gate conductance is dynamically adjusted through multiple word lines to control the Alpha ratio. During write operations, the gate conductance is increased to reduce the effective Alpha ratio and improve writeability, while during read operations, it is decreased to increase the effective Alpha ratio and maintain stability.
Solution Approach 2:
The conductance parameter is changed based on operation type through word line control. This allows dynamic optimization of the Alpha ratio - using higher conductance for writes (lower effective Alpha) and lower conductance for reads (higher effective Alpha), resolving the stability-writeability tradeoff.
4Ease of operation
If a lower Alpha ratio between transfer gate and storage device is used, then writeability is improved, but stability deteriorates
Solution Approach 1:
The transfer gate conductance is dynamically controlled through multiple word lines to adjust the Alpha ratio. During write operations, the gate conductance is increased to lower the effective Alpha ratio and improve writeability, while during read operations, it is decreased to raise the effective Alpha ratio and maintain stability.
Solution Approach 2:
The conductance parameter is dynamically changed based on operation type through word line control. This enables the system to use lower conductance (higher effective Alpha) for read stability and higher conductance (lower effective Alpha) for writeability, resolving the contradiction between stability and writeability.
Data Source
AI summary
A memory device comprises a bit cell comprising a bit storage device, a first word line, a second word line, and a first transfer gate to connect the bit storage device to a bit line. The first transfer gate is configurable to at least four conductance states based on a state of the first word line and a state of the second word line. The memory device further comprises control logic to configure, for an access to the bit cell, the state of the first word line and the state of the second word line based on an access type of the access.