Variable Dimension Conductive Patterns Sub-45nm Pitch
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Solution Overview
Problem
Conventional semiconductor device manufacturing techniques face challenges in scaling down metal features to pitches less than 45 nm, particularly in forming metal features of variable sizes and spacings, which are costly and require complex processes.
Innovation Solution
The method involves using immersion photolithography and multiple spacer deposition and etch acts to form conductive patterns with small, medium, and large segments of varying sizes and spacings, achieved through the use of hardmask portions and chop masks, allowing for the formation of complex patterns without the need for extreme ultraviolet lithography.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography techniques are used to form metal features, then the manufacturing process is simple, but the pitch is limited to about 80 nm and cannot achieve pitches less than 45 nm
Solution Approach 1:
The patterning process is divided into multiple discrete acts including forming first spacers on mandrels, removing mandrels, forming second spacers on remaining structures, and using chop masks to selectively remove portions. This segmentation allows achieving sub-45 nm pitch by breaking down the complex patterning into manageable steps, each with controlled precision requirements
Solution Approach 2:
The patent transitions from direct planar patterning to multi-layer spacer formation where patterns are built up in vertical layers. First spacers are formed on mandrels, then mandrels are removed, and second spacers are formed on the remaining structures. This vertical dimensionality enables pitch multiplication and achieves sub-45 nm features that cannot be obtained through conventional single-step photolithography
2Manufacturing precision
If double patterning techniques like SADP are used to reduce pitch, then the pitch can be reduced by up to one-half, but the process becomes more costly and requires numerous process acts
Solution Approach 1:
Instead of completing full multi-patterning cycles (such as complete quadruple or octuplet patterning), the patent applies partial patterning actions using chop masks that selectively remove only the necessary portions of spacers. This partial action achieves the required variable pitch and spacing patterns without executing the entire sequence of complex patterning steps, thereby reducing manufacturing cost while maintaining precision
3Manufacturing precision
If triple patterning, quadruple patterning, or octuplet patterning techniques are used to further scale down pitch, then the pitch can be reduced further, but the process becomes even more costly and complex
Solution Approach 1:
The patent performs preliminary patterning actions by forming spacers and using selective removal techniques before committing to full multi-patterning sequences. The chop mask technique allows preliminary definition of variable pitch regions, enabling subsequent steps to be simplified and avoiding the need for complete triple, quadruple, or octuplet patterning processes
4Manufacturing precision
If EUV lithography is used to form metal features at pitch of about 36 nm, then the pitch can be reduced to sub-45 nm, but the process requires numerous and complex process acts and is expensive
Solution Approach 1:
The patent uses spacer structures as copies or replicas of the desired final pattern. By forming spacers conformally on mandrels or existing structures and then selectively removing portions, the process creates copies of patterns at reduced pitch without requiring EUV lithography. This copying mechanism achieves sub-45 nm pitch using conventional lithography tools combined with multiple spacer formation and selective removal steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the cost-effective formation of conductive patterns with pitches less than 45 nm, reducing the complexity and expense of the manufacturing process while achieving the desired variability in segment sizes and spacings.
Implementation Method 1
a first spacer material is deposited over the mandrels and a second spacer material is deposited over the patterned first portion of the hardmask material
Data Source
AI summary
A metal pattern comprising interconnected small metal segments, medium metal segments, and large metal segments. At least one of the small metal segments comprises a pitch of less than about 45 nm and the small metal segments, medium metal segments, and large metal segments are separated from one another by variable spacing. Semiconductor devices comprising initial metallizations, systems comprising the metal pattern, and methods of forming a pattern are also disclosed.