Variable Size Convolution Circuit Using Cyclic Data Rotation
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Solution Overview
Problem
Current convolutional neural networks face inefficiencies in handling variable feature and kernel sizes, which can lead to suboptimal performance in convolutional computations due to fixed padding methods and limited parallel processing capabilities.
Innovation Solution
A circuit structure is developed for performing parallel convolutional computation, featuring a feature manager, kernel manager, and convolution engine that allows for variable feature and kernel sizes by using 0-padding convolutions, cyclic rotation of data, and controlled MAC operations, enabling efficient computation through restricted and compensated convolutions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If fixed padding methods are used in convolutional neural networks, then the computation structure is simplified, but the handling of variable feature and kernel sizes becomes inefficient
Solution Approach 1:
The patent implements dynamic padding and restriction mechanisms that adapt to variable feature and kernel sizes. The circuit uses control signals to dynamically adjust the padding applied to feature maps and kernels, and to restrict computations to valid regions, enabling efficient handling of different size configurations without fixed structure limitations
Solution Approach 2:
The invention changes key parameters including feature map size, kernel size, and padding amount based on input requirements. The system accepts variable-sized inputs and dynamically adjusts computation parameters to maintain efficiency across different size configurations, resolving the contradiction between structural simplicity and size adaptability
2Ease of manufacture
If traditional convolutional computation is used, then the implementation is straightforward, but parallel processing capabilities are limited
Solution Approach 1:
The patent segments the convolutional computation into multiple independent parallel processing units. Each unit handles specific feature map channels or kernel elements simultaneously, with results accumulated through adder trees. This segmentation enables high-degree parallelism while maintaining a relatively simple implementation through modular design
Solution Approach 2:
The invention exploits the channel dimension of feature maps and kernels to create parallel processing paths. By processing multiple channels simultaneously across multiple computation units, the system transforms a single-threaded sequential operation into a multi-dimensional parallel computation, significantly improving productivity
3Adaptability or versatility
If variable feature and kernel sizes are supported, then the adaptability of the neural network is improved, but the computation complexity increases
Solution Approach 1:
The patent designs a universal convolutional computation circuit that handles variable feature and kernel sizes through a unified architecture. The same computation units process different size configurations by accepting size parameters and adjusting their operation accordingly, avoiding the need for multiple specialized circuits and reducing overall system complexity
Solution Approach 2:
The invention introduces intermediary components including size detection units, padding control logic, and restriction signal generators that mediate between variable inputs and the core computation units. These intermediaries standardize the variable-sized inputs into a uniform processing format, reducing the complexity burden on the main computation path
4Measurement precision
If restricted convolution with compensation is implemented, then the accuracy of convolutional computation is improved, but the processing time increases
Solution Approach 1:
The patent performs preliminary padding of feature maps and kernels to their maximum required sizes before convolution computation. This preliminary action ensures that all subsequent restricted convolutions operate on uniformly sized data, eliminating the need for repeated size adjustments and reducing overall processing time while maintaining accuracy
Solution Approach 2:
The invention maintains continuous computation flow by using accumulation registers that continuously sum partial convolution results across all restricted regions. Rather than completing one restricted convolution sequentially, the system performs multiple restricted convolutions in parallel with continuous accumulation, reducing processing time while preserving computational accuracy
Data Source
AI summary
A circuit for performing parallel convolutional computation for features and kernels of variable sizes may receive inputs of an m×n matrix of feature data, an m×n matrix of convolution data, and a (2m−1)×(2n−1) matrix of kernel data. A feature manager of the circuit may hold m rows of n data buffers storing the input feature data and rotating values between rows during one restricted convolution calculation. A kernel manager of the circuit may hold a (2m−1)×(2n−1) matrix of data buffers storing the input kernel data in the buffers and cyclically rotating values in upwards, downwards, leftwards and rightwards directions for different restricted convolution calculations. A row convolution engine of the circuit may hold m row convolution processors, each storing and updating input convolution data by multiplication-and-accumulation (MAC) operations on its input feature and kernel data rows. The circuit produces accumulated convolutional data.