Variable Decimation Rate for PLC Signal Phase Synchronization
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Solution Overview
Problem
Data communication between a command center and thousands of endpoint devices over power distribution lines is challenging due to issues such as endpoint processing power, memory size, and interference from alternating current (AC) power, which complicates digital signal processing.
Innovation Solution
A circuit-based apparatus with a transceiver circuit configured to communicate over power distribution lines using AC, featuring an analog-to-digital converter (ADC) module, a decimator module, and a reference signal generator to adjust the decimation rate and counteract phase differences, ensuring tight correlation between signal frequencies and processing, particularly using FFT-based processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If FFT-based processing is used with fixed sample rate, then processing simplicity is improved, but signal correlation deteriorates due to AC frequency variations
Solution Approach 1:
The patent implements a variable decimation rate in the decimator module that dynamically adjusts based on detected AC frequency variations. This allows the signal processing system to adapt to changing power line frequencies while maintaining proper correlation between the transmitted signal frequencies and the processing sample rate, thereby resolving the contradiction between processing simplicity and signal correlation reliability.
2Productivity
If decimation rate is increased to reduce processing load, then productivity is improved, but phase synchronization deteriorates
Solution Approach 1:
The patent employs a feedback mechanism where the system continuously detects phase differences between the reference signal and the actual AC signal, then adjusts the decimation rate accordingly. This closed-loop control ensures that productivity is improved through efficient decimation while phase synchronization is maintained through real-time adjustments based on detected phase errors.
3Productivity
If densely-packed frequency channels are used to increase bandwidth utilization, then productivity is improved, but spectral leakage increases
Solution Approach 1:
The patent maintains orthogonality between densely-packed frequency channels by dynamically adjusting the decimation rate to match AC frequency variations. This parameter adjustment ensures that the processing sample rate remains correlated with the transmitted signal frequencies, preventing spectral leakage even when using densely-packed channels for high bandwidth utilization.
Data Source
AI summary
Aspects of the present disclosure are directed toward receiver devices and methods of using receiver devices. One such method can include converting, using an analog-to-digital converter (ADC), and an analog input signal from power distribution lines that carry power using alternating current (AC) to a digital form. This input digital signal can be an oversampled digital signal, where the digital signal is oversampled relative to downstream processing (e.g., FFT-based processing). A processing circuit(s) can then be used to decimate the input digital signal according to a decimation rate. A reference signal can be generated by the processing circuit that is responsive to the decimation rate. The processing circuit can also be used to detect a change in a phase difference between the AC and reference signal and to modify, in response to detecting a change in the phase difference, the decimation rate to counteract the detected change in the phase difference.