Variable Decimation Feedback Shift Register for Cryptographic Security
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Solution Overview
Problem
Existing cryptographic algorithms using feedback shift registers for key bit stream generation are vulnerable to attacks, particularly known plaintext attacks, and increasing hardware resources to enhance security is costly and impractical for mass-produced cryptographic devices.
Innovation Solution
Implementing a decimator to select every mth bit of the bit sequence generated by a feedback shift register, with a readjustable decimation value, to create a variable key bit stream that appears to come from a different encryption device, thereby increasing security without significant hardware additions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of shift registers or their size is increased to raise security level, then security is improved, but hardware costs increase unacceptably
Solution Approach 1:
The patent applies parameter changes by modifying the decimation value m, which is a numerical parameter controlling the sampling rate of the shift register output. By dynamically changing m between different values (e.g., m1 and m2), the system creates multiple apparent key bit stream patterns from a single shift register configuration, effectively increasing security without adding hardware components. This resolves the contradiction by achieving higher reliability through parameter variation rather than hardware expansion.
2Reliability
If multiple feedback shift registers are used simultaneously to generate key bit stream, then security is improved, but device complexity and manufacturing costs increase
Solution Approach 1:
The patent applies segmentation by dividing the key bit stream generation process into two distinct phases: a first phase using decimation value m1 and a second phase using decimation value m2. This temporal segmentation allows a single shift register to perform the work of multiple registers, reducing manufacturing complexity while maintaining security through phase-based operation. The segmentation of the generation process into multiple phases with different parameters achieves the security of multiple registers without their hardware overhead.
Solution Approach 2:
The patent applies dynamics by making the decimation value m dynamic rather than static. The system transitions between different decimation values (m1, m2) at different times or under different conditions, creating a dynamic key bit stream generation process. This dynamic behavior increases security against cryptographic attacks while using a single, simple shift register structure, thereby easing manufacturing requirements.
3Device complexity
If a single feedback shift register is used to generate key bit stream, then hardware costs are reduced, but security level decreases
Solution Approach 1:
The patent applies universality by making the single feedback shift register perform multiple functions through varying the decimation value m. The same physical register generates different apparent key bit streams by changing the sampling rate parameter m between phases. This multi-functionality allows one component to replace what would traditionally require multiple components, reducing hardware costs while maintaining security through parameter-based differentiation.
Data Source
AI summary
A bit sequence which is generated by a feedback shift register is decimated with a variable decimation value m (mε|N) in a predetermined manner which is known on the decryption side, i.e. in that every mth bit of the bit sequence is picked out from the bit sequence so as to obtain the key bit stream.