Variable Delay Circuit for DRAM Signal Synchronization
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Solution Overview
Problem
As semiconductor devices become more highly integrated, internal signal path mismatches can lead to malfunctions during changes in the external environment, affecting precise read and write operations in DRAM devices.
Innovation Solution
Incorporating a variable delay circuit and an address latch circuit that adjust delay times based on feedback signals to synchronize read signals with address logic levels during initialization, preventing signal mismatch during operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells is increased to achieve higher integration, then the storage capacity is improved, but signal path mismatches occur causing malfunctions
Solution Approach 1:
The patent applies dynamics by making the delay time adjustable rather than fixed. The delay circuit dynamically adjusts the timing of the read signal based on feedback from the address latch circuit, allowing the system to adapt to variations in signal paths caused by increased integration. This resolves the contradiction by enabling the system to maintain reliability despite the quantity of memory cells increasing.
Solution Approach 2:
The patent implements feedback by having the address latch circuit generate a feedback signal based on whether the read signal and address logic level are matched, and using this feedback to adjust the delay time in the delay circuit. This closed-loop feedback mechanism ensures that signal path mismatches are detected and corrected, maintaining reliability as the number of memory cells increases.
2Device complexity
If fixed delay time is used for read signal, then the circuit complexity is reduced, but signal mismatch occurs during initialization
Solution Approach 1:
The patent transitions from a static fixed delay time to a dynamic adjustable delay time. The delay circuit can modify its delay characteristics based on feedback signals, allowing precise timing adjustment during initialization without requiring overly complex circuitry. This dynamic approach achieves reliability while keeping the overall circuit complexity manageable.
Solution Approach 2:
The patent applies parameter changes by adjusting the delay time parameter of the read signal based on feedback from the address latch circuit. Instead of using a fixed delay parameter, the system dynamically modifies the delay time to match the actual timing requirements during initialization, improving address latch accuracy without proportionally increasing circuit complexity.
3Measurement precision
If delay time is adjusted during initialization, then signal matching precision is improved, but the initialization process becomes more complex
Solution Approach 1:
The patent uses feedback to simplify the initialization process. The address latch circuit generates a feedback signal that automatically indicates whether timing adjustment is needed, and the delay circuit adjusts its delay time accordingly. This automated feedback-driven adjustment achieves high signal timing precision without requiring complex manual initialization procedures or additional control logic.
Solution Approach 2:
The system performs self-service by automatically adjusting its own timing parameters during initialization without external intervention. The feedback signal from the address latch circuit triggers the delay circuit to self-correct timing mismatches, achieving precise signal matching while keeping the initialization process simple and autonomous.
Data Source
AI summary
A semiconductor device includes a variable delay circuit and an address latch circuit. The variable delay circuit delays a read signal by a delay time to generate a latch control signal during an initialization operation and receives a feedback signal to adjust the delay time for delaying the read signal during the initialization operation. The address latch circuit detects a logic level of a transfer address when the latch control signal is inputted to the address latch circuit and generates the feedback signal.