Variable Delay Circuit for Semiconductor Memory Speed Optimization
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Solution Overview
Problem
Semiconductor memory devices face challenges in adjusting charge sharing time due to parasitic capacitances, which limits operating speed and requires fixed RC delay circuits, restricting high-speed performance.
Innovation Solution
A semiconductor memory device with a variable delay circuit that adjusts bitline charge sharing time by varying the slope of a delay voltage based on external power supply voltage, using a combination of resistors and switches to control the delay voltage adjuster and maintain uniform or reduced charge sharing time as needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed RC delay circuit is used to ensure adequate charge sharing time, then reliability is improved, but operating speed is limited
Solution Approach 1:
The patent implements a variable delay circuit that dynamically adjusts the delay time based on operating conditions. The delay circuit transitions from a fixed RC implementation to a controllable delay mechanism that can adapt its timing characteristics, allowing the system to optimize between reliability (adequate charge sharing) and speed (faster operations) based on real-time requirements
Solution Approach 2:
The patent changes the delay parameter from a fixed value to a variable value that can be adjusted based on external power supply voltage and operational mode. By making the delay time a可调 parameter rather than a fixed constant, the system can shorten delay during high-speed operations while maintaining adequate delay when reliability is prioritized
2Productivity
If cell capacitors are made smaller to increase density, then productivity is improved, but charge sharing time requirements worsen due to increased parasitic capacitance effects
Solution Approach 1:
The variable delay circuit dynamically compensates for the increased parasitic capacitance effects in smaller cell capacitors by adjusting the delay time based on the specific operational conditions and power supply voltage, allowing small capacitors to maintain adequate charge sharing without excessive delay penalties
3Speed
If a variable delay circuit is implemented to improve operating speed, then speed is improved, but device complexity increases
Solution Approach 1:
The delay circuit is designed to serve multiple functions: it provides delay adjustment for speed optimization, adapts to different power supply voltage conditions, and maintains reliability across varying operational modes. This multi-functionality justifies the increased complexity by delivering comprehensive performance benefits beyond simple delay adjustment
Data Source
AI summary
A semiconductor memory device comprises a memory cell configured to output data to a pair of bitlines, a variable delay circuit configured to receive a sense amplifier enable signal, adjust a delay of the sense amplifier enable signal by changing a slope of a delay based on a variable external power supply voltage, and output a delayed sense amplifier enable signal, and a bitline sense amplifier configured to amplify a voltage difference between the pair of bitlines in response to the delayed sense amplifier enable signal and output the amplified voltage difference to a pair of input/output lines.