Variable Delay Clock Circuit for High-Resolution Phase Offset
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Solution Overview
Problem
Existing clock generation systems face challenges in achieving high resolution phase delay without requiring complex phase multiplexers, particularly in integrated circuits, and struggle to generate variable delay clocks with high precision.
Innovation Solution
A delay clock synthesizer (DLCS) system that includes a phase detector, summing circuit, loop filter, and voltage-controlled delay line, utilizing a finite-state machine and dual variable delay clock circuits to generate an output clock with controlled phase offset, allowing for high resolution and unbounded phase delay without the need for a high complexity phase multiplexer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a clock multiplexer is used to generate variable phase clock, then phase delay capability is improved, but device complexity increases significantly
Solution Approach 1:
The patent divides the delay function into multiple identical delay cells (N delay elements) that can be independently controlled. Each delay cell provides a fixed delay amount, and by selectively enabling different combinations of these cells through simple binary control signals, the system achieves variable phase delay without requiring a complex multiplexer. This segmentation transforms a single complex phase selection problem into multiple simple delay accumulation problems.
2Measurement precision
If the number of delay stages is increased to achieve high resolution phase delay, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent changes the control parameter from analog phase selection (requiring complex multiplexers) to digital delay cell selection. By assigning binary weights to control signals (2^0, 2^1, 2^2, ..., 2^(N-1)), the system achieves fine phase resolution through simple digital combinations. This parameter transformation allows high-resolution phase control using only simple delay elements and binary logic, avoiding complex analog phase multiplication circuits.
3Adaptability or versatility
If a traditional DLL with phase multiplexer is used, then variable phase clock generation is achieved, but ease of manufacture deteriorates due to integration difficulties
Solution Approach 1:
The patent uses multiple identical copies of simple delay cell circuits instead of a single complex multiplexer circuit. Each delay cell is a replicated, standardized unit that can be easily fabricated using standard CMOS processes. This copying approach simplifies manufacturing by replacing difficult-to-fabricate high-frequency multiplexers with numerous identical, easy-to-fabricate delay elements, improving yield and reducing fabrication complexity.
Data Source
AI summary
An apparatus for generating an output clock is disclosed. The apparatus comprises: N variable offset clock circuits for receiving N input clocks and for generating N intermediate clocks having N phase offsets controlled by N intermediate signals, respectively, where N>1; a clock multiplexer for selecting one of the N intermediate clocks as the output clock according to a finite-state signal having N possible states; and a finite-state-machine for receiving a control signal and the N intermediate clocks and for generating the finite-state signal and the N intermediate signals.