Variable Delay Column Command Buffer for Semiconductor Memory
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Solution Overview
Problem
Conventional semiconductor memory apparatuses face challenges in generating internal column commands and read/write signals accurately across varying clock frequencies, leading to potential misoperations, especially at low frequencies.
Innovation Solution
A column command buffer with a variable delay section that adjusts delay times based on clock frequency, coupled with a buffering section to generate internal column commands, and a latency unit that ensures proper timing for internal read/write signals by employing flip-flops and pass gates to manage additive and CAS write latencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional column command buffer uses fixed delay timing, then the circuit structure is simple, but the internal column commands cannot be generated accurately at varying clock frequencies especially low frequencies
Solution Approach 1:
The patent implements a variable delay section that dynamically adjusts the delay time of the column command based on the detected clock frequency. When the clock frequency is low, the delay time is increased to ensure accurate generation of internal column commands. This dynamic adjustment resolves the contradiction by making the delay parameter adaptable rather than fixed, thereby maintaining reliability across different operating conditions without requiring completely separate circuits for each frequency range.
Solution Approach 2:
The patent changes the delay time parameter of the column command buffer based on the clock frequency. A frequency detection section monitors the clock frequency and controls the variable delay section to adjust the delay time accordingly. This parameter change approach allows the system to maintain accurate internal column command generation at varying frequencies while using a single unified circuit structure, thus improving reliability without proportionally increasing device complexity.
2Reliability
If the delay time is increased to accommodate low clock frequencies, then accurate internal command generation is achieved, but the CAS latency increases
Solution Approach 1:
The patent uses a variable delay section that dynamically adjusts the delay time based on clock frequency detection. When the clock frequency is high, the delay time is reduced to minimize CAS latency. When the clock frequency is low, the delay time is increased to ensure accurate internal read signal generation. This dynamic adjustment resolves the contradiction by optimizing the delay parameter for each operating condition, thereby minimizing time loss while maintaining reliability.
Solution Approach 2:
The patent changes the delay time parameter according to the detected clock frequency to balance between accuracy and speed. The frequency detection section monitors the clock frequency and controls the variable delay section to adjust the delay time, thereby minimizing CAS latency at high frequencies while ensuring accurate internal read signal generation at low frequencies. This parameter adaptation resolves the contradiction between reliability and time loss.
3Reliability
If flip-flops and pass gates are used to manage latencies, then proper timing control is achieved, but the device complexity increases
Solution Approach 1:
The patent segments the latency control function into distinct modules: a frequency detection section, a variable delay section, and a buffering section with flip-flops and pass gates. Each module performs a specific function, making the overall complex system manageable and maintainable. The segmentation allows proper timing control to be achieved through coordinated operation of specialized sub-circuits rather than a monolithic complex circuit.
Solution Approach 2:
The patent introduces a frequency detection section as an intermediary that monitors the clock frequency and controls the variable delay section. This intermediary component enables the system to adapt to varying clock frequencies and maintain accurate timing without requiring manual intervention or complex hard-wired logic. The frequency detection section acts as a mediator between the clock signal and the delay control mechanism, simplifying the overall control architecture.
Data Source
AI summary
A column command buffer includes a variable delay section configured to determine a delay time based on a frequency of a clock, and output a column command after delaying it by the delay time; and a buffering section configured to receive an output of the variable delay section and generate internal column commands.