Variable Delay Circuit With Dummy MOS Switching for Linear DTC Timing
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Solution Overview
Problem
Variable delay circuits face nonlinearity issues due to the influence of drain capacitance, which affects the accuracy of delay control, especially when MOS switches transition between on and off states, leading to significant integral nonlinearity errors.
Innovation Solution
A variable delay circuit design that includes a controller supplying a valid control code for delay and a dummy code to stabilize the drain capacitance by turning on all MOS switches before the delay edge, ensuring consistent capacitance and reducing nonlinearity errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the capacitance C of the capacitor is reduced to increase the resolution of the DTC circuit, then the resolution is improved, but the influence of drain capacitance Cd becomes significant and causes nonlinearity errors
Solution Approach 1:
The patent applies preliminary action by turning on dummy MOS switches before the actual delay operation to pre-establish stable capacitance conditions. The dummy switches are activated in advance to charge or discharge the drain capacitance, ensuring that when the actual delay begins, the capacitance is already stabilized and won't cause nonlinearity errors during the critical delay period.
Solution Approach 2:
The patent changes the operational parameters of the MOS switches by introducing a two-stage control mechanism: first activating dummy switches to stabilize capacitance parameters, then switching to the actual delay-configured switches. This parameter transformation allows the system to operate with reduced capacitor capacitance while maintaining stable drain capacitance characteristics throughout the delay process.
2Loss of time
If MOS switches are turned off to reduce capacitance for delay control, then the delay amount increases, but the drain capacitance becomes undefined and causes integral nonlinearity errors
Solution Approach 1:
The patent introduces dummy MOS switches as intermediary elements that mediate between the power supply and the drain capacitance. These dummy switches serve as a buffer that stabilizes the drain voltage potential before the actual delay operation begins, preventing the drain capacitance from becoming undefined when the main switches are turned off for delay control.
Solution Approach 2:
The patent applies beforehand cushioning by using dummy switches to pre-stabilize the drain capacitance condition before the actual delay operation. This cushioning action ensures that even when main switches are turned off to achieve the desired delay, the drain capacitance remains well-defined and stable, preventing nonlinearity errors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively stabilizes the capacitance and reduces nonlinearity errors, enabling the generation of pulses with small jitter and improved delay accuracy.
Implementation Method 1
The plurality of capacitors C1 to CN and the plurality of MOS switches M1 to MN are used. One ends of the plurality of capacitors C1 to CN are connected to the delay line 106. The plurality of MOS switches M1 to MN are provided between the other ends of the corresponding capacitors C1 to CN and the ground, respectively.
Implementation Method 2
Each bit of the control code DTC_CODE designates on/off of the corresponding MOS switch. When the capacitance values of the capacitors C1 to CN are equal (Cu) and the M MOS switches are in the on state, the total capacitance CDELAY effectively connected to the delay line 106 is Cu×N.
Implementation Method 3
When the capacitance C of the capacitor decreases, the influence of a drain capacitance Cd of the MOS switch M cannot be ignored relatively. When the MOS switch M1 is off, the capacitance seen from the delay line 106 is a combined capacitance (CU*Cd)/(CU+Cd) of the series connection of C and Cd. Here, the drain capacitance Cd is sufficiently smaller than the capacitance C of the capacitor (CU).
Data Source
AI summary
A variable delay circuit, which includes a digital-to-time converter (DTC) circuit and a controller, is disclosed. The DTC circuit includes a plurality of capacitors and a plurality of MOS switches that are turned on and off according to a control code. The DTC circuit receives an input pulse, applies a delay corresponding to the control code to the edge to be delayed, and outputs a delay pulse. The controller supplies a valid code indicating a delay amount as a control code during a period beginning from a predetermined time TCONST before the edge (positive edge) to be delayed of an input pulse REF up to the edge to be delayed. Further, the controller supplies, as the control code, a dummy code for turning on all of the plurality of MOS switches inside the DTC circuit immediately before the period.