Variable-Delay FIR Filter for Reflection Ripple Equalization
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Solution Overview
Problem
High-speed data converters experience signal degradation due to impedance mismatches causing standing waves and frequency ripple, which traditional FIR filters become inefficient and resource-intensive to address as the length of transmission media and data speed increase.
Innovation Solution
Implementing multiple filters with variable integer sample delays and gain components in parallel paths to compensate for specific reflections, reducing the number of taps and computational requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single large FIR filter is used to equalize frequency ripple in high-speed data converters, then signal quality is improved, but device complexity and computational requirements increase significantly
Solution Approach 1:
The patent divides a single large FIR filter into multiple smaller parallel FIR filters with different numbers of taps. Each filter processes a specific frequency range or reflection component, and their outputs are combined. This segmentation reduces the computational complexity of each individual filter while maintaining the overall equalization performance needed to correct frequency ripple and standing waves in high-speed data converter signals.
2Reliability
If the number of taps in FIR filter is increased to handle longer transmission media, then equalization effectiveness is improved, but power consumption and area increase
Solution Approach 1:
Instead of using one large FIR filter with many taps that consumes high power, the patent segments the filtering function into multiple parallel filters with fewer taps each. The combined output of these smaller filters achieves the same equalization effectiveness for long transmission media while consuming less power individually and collectively, making the solution scalable for different transmission distances.
Solution Approach 2:
The patent applies different numbers of taps to different parallel filters based on their specific functions. Some filters have more taps for handling specific reflection components or frequency ranges, while others have fewer taps. This local optimization ensures that computational resources and power are allocated efficiently to where they are most needed, rather than uniformly across all filter paths.
3Reliability
If traditional FIR filter is used for high-speed data conversion, then signal equalization is achieved, but computational requirements and processing time increase
Solution Approach 1:
The patent parallelizes the filtering operation by using multiple FIR filters simultaneously processing different aspects of the signal. This parallel architecture enables signal equalization to be performed faster than a single sequential filter, improving processing speed for high-speed data conversion applications while maintaining effective equalization performance.
Data Source
AI summary
In an example, a circuit includes a first signal path including a first filter having a first number of taps and having an input and an output. The circuit also includes a combiner having first and second inputs, the first input coupled to the output of the first filter. The circuit includes a second signal path coupled to the input of the first filter and to the second input of the combiner. The second signal path includes a gain component, a delay component coupled to the gain component, and a second filter having a second number of taps and coupled to the delay component.