Variable Delay Circuit Layout for Wide-Range High-Frequency Timing
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Solution Overview
Problem
Existing variable delay circuits in semiconductor integrated circuits face challenges in generating a delay amount corresponding to the maximum operating frequency due to the minimum delay limitation of the coarse adjustment block, which restricts their ability to adjust a wide range of delay values accurately.
Innovation Solution
The proposed solution involves a variable delay circuit configuration with multiple delay elements of different time durations, where the first delay elements have a shorter time duration and the second delay elements have a longer time duration, allowing for precise adjustment by connecting them in series and controlling their states to achieve a wide range of delay amounts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a coarse adjustment block with a fixed minimum delay amount is used, then the circuit structure is simplified, but the delay range cannot cover the maximum operating frequency requirement
Solution Approach 1:
The delay circuit is divided into multiple independent delay units, each capable of being selectively activated. This segmentation allows the circuit to achieve variable delay ranges by combining different delay units, resolving the contradiction between simplified structure and extended delay range.
Solution Approach 2:
The delay circuit transitions from a fixed minimum delay structure to a dynamic structure where delay units can be selectively enabled or disabled based on operating frequency requirements. This dynamic configuration allows the delay range to adapt to different frequency conditions while maintaining a relatively simple base circuit structure.
2Measurement precision
If the minimum delay amount is determined by the coarse adjustment block, then the fine adjustment block can provide precise control, but the overall minimum delay cannot be reduced below the coarse block's delay
Solution Approach 1:
The delay circuit is divided into multiple independent delay units, each capable of being selectively activated. This segmentation allows the circuit to achieve variable delay ranges by combining different delay units, resolving the contradiction between simplified structure and extended delay range.
Solution Approach 2:
The delay circuit transitions from a fixed minimum delay structure to a dynamic structure where delay units can be selectively enabled or disabled based on operating frequency requirements. This dynamic configuration allows the delay range to adapt to different frequency conditions while maintaining a relatively simple base circuit structure.
Data Source
AI summary
A variable delay circuit includes at least one first delay circuit and a second delay circuit. The first delay circuit includes multiple first delay elements connected in series and is configured to output a delay signal from a first stage first delay element that is a first stage of the first delay circuit. The second delay circuit includes at least one second delay element and multiple third delay elements connected in series. The second delay circuit is configured to output a delay signal from a first stage second delay element that is a first stage of the second delay circuit. The first stage first delay element and the first stage second delay element are connected in series. A delay signal obtained by delaying an input signal received at one circuit among the first delay circuit and the second delay circuit for a predetermined time duration is output from another circuit.