Variable Delay Circuit with Segmented Stages for Low Power
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Solution Overview
Problem
Conventional delay circuits require a large number of shift registers and selection circuits to achieve desired latency, leading to increased circuit size and power consumption, which is counterintuitive to low power requirements in modern digital circuit design, especially as clock frequency increases.
Innovation Solution
A variable delay circuit comprising a fixed delay unit, a first selection unit, and a variable delay unit, where the fixed delay unit provides a fixed delay and the variable delay unit offers adjustable delay, utilizing fewer components to achieve 0 to 16 unit delays with reduced selection signals and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a large number of shift registers are used to achieve desired latency, then the latency control range is improved, but the circuit size and power consumption increase
Solution Approach 1:
The delay circuit is divided into multiple stages, each providing a portion of the total delay. Instead of using one large shift register, the circuit uses several smaller delay stages (e.g., 4 stages with 2 bits each) that can be selectively activated. This segmentation reduces the number of components needed while maintaining the same latency control range.
Solution Approach 2:
The circuit dynamically activates only the necessary delay stages based on the required latency value. Control logic selectively enables or disables specific delay stages, so that not all shift registers need to be active simultaneously. This dynamic activation reduces power consumption while maintaining full latency control capability.
2Loss of time
If the number of shift registers is increased to achieve longer latency, then the maximum latency is improved, but the selection circuit size increases
Solution Approach 1:
The selection process is segmented into multiple smaller selection operations. Instead of selecting from all delay elements simultaneously, the circuit performs hierarchical selection - first selecting which stages to activate, then selecting the specific delay within each stage. This reduces the complexity of any single selection circuit while achieving the same functionality.
Solution Approach 2:
The patent introduces a hierarchical control structure with multiple dimensions of selection. Rather than a single flat selection from n elements, the system uses multi-level control signals that select across different stages and within stages, effectively adding dimensional complexity to manage the selection process more efficiently.
3Adaptability or versatility
If all delay elements are turned on to control latency from 0 to n clock cycles, then the latency flexibility is improved, but the power consumption increases
Solution Approach 1:
The circuit dynamically controls the activation state of each delay stage based on the required latency. Control logic determines which stages need to be active and disables others, creating a dynamic power management system that maintains latency flexibility while minimizing power consumption by activating only necessary components.
Solution Approach 2:
The circuit selectively disables (discards) unused delay stages to reduce power consumption, and can re-enable (recover) them when needed. This selective activation/deactivation mechanism allows the system to maintain full latency flexibility while consuming power only for the portions of the circuit currently in use.
Data Source
AI summary
A variable delay circuit includes at least a fixed delay unit, a first selection unit, and variable delay unit. The fixed delay unit receives an input signal and a first delay selection signal indicative of a first delay, and outputs a first delayed signal that is substantially the input signal delayed by the first delay. The first selection unit receives the input signal, the first delayed signal, and a second delay selection signal, and outputs either the input signal or the first delayed signal based on the second delay selection signal to the variable delay unit. The variable delay unit also receives a third delay selection signal indicative of a third delay, and outputs a output signal that is substantially the output signal of the selection unit delayed by a third delay. The first delay is 0 or X multiples of M delay units. The third delay is a delay selected from 0 to N delay units.