Variable Delay Unit for Semiconductor Memory Timing
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Solution Overview
Problem
Semiconductor memory devices face timing errors due to differences in data signal delays between data training mode and normal operating mode, as compensation patterns developed during training may not align with actual operating conditions.
Innovation Solution
A semiconductor memory device with a variable delay unit that adjusts data signal delays based on whether it is in data training mode or normal operating mode, using a data trainer to compare signals with predetermined patterns and a memory controller to manage these adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data training is performed in a different operating environment than normal operation, then data training can be completed, but timing errors occur during normal operation due to mismatched compensation patterns
Solution Approach 1:
The patent applies dynamics by making the delay amount variable based on operating mode. The variable delay unit dynamically adjusts the delay applied to data signals depending on whether the device is in data training mode or normal operating mode. This resolves the contradiction by allowing the system to adapt its timing characteristics to match the current operating environment, ensuring accurate compensation in both training and normal operation without timing errors.
2Ease of operation
If fixed delay compensation is applied during data training, then training can proceed, but the compensation is inaccurate for normal operation due to environmental differences
Solution Approach 1:
The patent applies parameter changes by modifying the delay parameter based on operating mode. The variable delay unit changes the delay parameter from a fixed value to a mode-dependent value, where different delay amounts are applied during data training mode versus normal operating mode. This resolves the contradiction by allowing the system to maintain operational simplicity while achieving precise delay compensation tailored to each specific operating environment.
Data Source
AI summary
A semiconductor memory device comprises a variable delay unit and a data trainer. The variable delay unit is configured to generate a write data signal by delaying a write data driving signal by different amounts of time depending on whether the semiconductor memory device is in a data training mode or a normal operating mode, and further configured to generate a read data driving signal by delaying a read data signal by different amounts of time in the data training mode and the normal operating mode. The data trainer is configured to be activated in the data training mode, and while activated, receive the write data signal, compare the write data signal with a predetermined write pattern, perform a data training mode operation, and output the read data signal with a predetermined read pattern.