Variable Delay Unit for Stacked Memory Signal Skew
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Solution Overview
Problem
The existing stacked semiconductor memory apparatuses face issues with signal skew due to PVT variations, leading to reduced timing margins and operational deterioration, particularly in high-speed operations, as multiple slave chips share a single path for data and timing signals, affecting data transmission characteristics.
Innovation Solution
Incorporating a variable delay unit that detects PVT variations in each slave chip and generates a delay timing signal to adjust the first timing signal, allowing the timing signal generation unit to produce synchronized second timing signals, thereby reducing skew and increasing timing margins by compensating for process-related delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multiple slave chips share a single path for timing signals, then device complexity is reduced, but signal skew increases due to PVT variations
Solution Approach 1:
The patent changes the delay parameter of each slave chip dynamically based on detected PVT variations. Each slave chip includes a delay unit that adjusts its signal delay time according to process, voltage, and temperature conditions, thereby compensating for skew without requiring separate physical paths for each chip.
Solution Approach 2:
The patent implements a feedback mechanism where each slave chip detects its own PVT variations and uses this information to adjust its delay time. The delay unit receives feedback about the actual timing skew and modifies the delay parameter accordingly to maintain synchronized operation across all slave chips.
2Reliability
If delay time is increased to compensate for PVT variations, then timing margin is improved, but operation speed decreases
Solution Approach 1:
The patent makes the delay time dynamic rather than fixed. Each slave chip adjusts its delay parameter in real-time based on detected PVT variations, allowing the system to maintain adequate timing margins only when necessary while preserving high-speed operation under normal conditions. This dynamic adjustment prevents the permanent speed penalty that would result from a fixed conservative delay setting.
3Reliability
If separate paths are provided for each slave chip, then signal skew is reduced, but device complexity and area increase
Solution Approach 1:
Instead of providing separate physical paths, the patent changes the delay parameter of each slave chip to compensate for transmission differences. This parameter-based compensation approach achieves the timing alignment benefits of separate paths while maintaining the area and complexity advantages of a shared path architecture.
Data Source
AI summary
The semiconductor apparatus includes a reference delay value check unit configured to receive a source signal and delay the source signal to generate a reference delay signal; a process delay value check unit configured to receive the source signal and delay the source signal to generate a process delay signal; and a signal generation unit configured to receive the reference delay signal and the process delay signal, receive an input signal, and variably delay the input signal based on the reference delay signal and the process delay signal to generate an output signal.