Variable Delay Word Line Enable Circuit for SRAM
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Solution Overview
Problem
In large memory arrays, such as SRAM devices, the uniform delay of word line enable signals leads to performance degradation due to varying distances from the control block, causing slower access times for word lines farther away, resulting in data errors during read and write operations.
Innovation Solution
A variable delay circuit is implemented to adjust the delay time of word line enable signals based on the address of selected word lines, ensuring bit lines are fully precharged before assertion, with shorter delays for closer word lines and longer delays for farther ones to account for signal propagation time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If uniform delay is applied to all word line enable signals, then circuit design is simplified, but access time performance deteriorates for word lines farther from the control block
Solution Approach 1:
The patent applies different delay values to different word line enable signals based on their distance from the control block. Word lines closer to the control block receive shorter delays, while those farther away receive longer delays, optimizing access time for each local region of the memory array.
Solution Approach 2:
The delay value is made dynamic and variable rather than fixed. The delay circuit selectively applies different delay amounts based on which word line is being accessed, allowing the system to adapt the timing characteristics to the specific operational requirements of each word line.
2Reliability
If longer delay is applied to distant word lines to account for signal propagation, then read/write reliability is improved, but overall access time increases
Solution Approach 1:
The patent provides the minimum necessary delay for each word line based on its specific distance from the control block, rather than applying a uniform excessive delay to all word lines. This ensures reliable data transfer while minimizing the time penalty.
Solution Approach 2:
The delay is applied in advance to the word line enable signal to ensure that bit lines are fully precharged before the word line is asserted, preventing data errors while using the exact amount of delay needed.
3Speed
If variable delay circuit is implemented, then access time optimization is achieved, but device complexity increases
Solution Approach 1:
The patent divides the memory array into multiple segments or groups, with each group having a specific delay value assigned to its word line enable signals. This segmentation approach allows optimization of access times while limiting the number of different delay values that must be implemented.
Data Source
AI summary
A memory device includes a bit line precharge circuit configured to precharge bit lines of a memory array in response to a clock pulse. A controller is configured to output the clock pulse to the bit line precharge circuit, and to output a first word line enable signal to a word line driver. The first word line enable signal is delayed by a first delay time from the clock pulse, and a second word line enable signal is delayed by a second delay time from the clock pulse.