Variable Delay Word Line Enable Circuit for Memory Arrays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In large memory arrays, such as SRAM devices, the uniform delay of word line enable signals leads to performance degradation due to varying distances from the control block, causing slower access times for word lines farther away, resulting in data errors during read and write operations.
Innovation Solution
A variable delay circuit is implemented to adjust the delay time of word line enable signals based on the address of selected word lines, ensuring bit lines are fully precharged before assertion, with shorter delays for closer word lines and longer delays for farther word lines to account for signal propagation time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If uniform delay is applied to all word line enable signals, then device complexity is reduced, but access time performance deteriorates for word lines farther from the control block
Solution Approach 1:
The patent applies different delay values to different word line enable signals based on their physical distance from the control block. Word lines farther away receive longer delays while closer word lines receive shorter delays, optimizing access time for each local region rather than applying a uniform delay across the entire array.
Solution Approach 2:
The patent segments the word line array into multiple groups based on distance from the control block, with each group receiving a specific delay value. This segmentation allows the system to manage complexity by dividing the large array into manageable segments while still achieving optimized performance for each segment.
2Reliability
If longer delay is applied to farther word lines to account for signal propagation, then read/write operation reliability is improved, but overall operation speed deteriorates
Solution Approach 1:
The patent changes the delay parameter dynamically based on the selected word line address. The delay circuit receives the word line address and adjusts the delay value accordingly, ensuring that each word line gets the precise delay needed for reliable operation without adding excessive time to the overall cycle.
Solution Approach 2:
The delay is applied preliminarily to the word line enable signal before the actual read/write operation begins. This preliminary timing adjustment ensures that bit lines are fully precharged and ready before the word line is activated, preventing data errors without extending the critical path of the operation.
Data Source
AI summary
A memory device includes a bit line precharge circuit configured to precharge bit lines of a memory array in response to a clock pulse. A controller is configured to output the clock pulse to the bit line precharge circuit, and to output a first word line enable signal to a word line driver. The first word line enable signal is delayed by a first delay time from the clock pulse, and a second word line enable signal is delayed by a second delay time from the clock pulse.