Variable-Diameter Nanosheet Gate Electrodes for Short-Channel Control
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in achieving further improvements in nanosheet FETs to address scaling down issues, particularly in maintaining device performance and reducing manufacturing costs while ensuring effective gate control and minimizing short-channel effects.
Innovation Solution
A semiconductor device structure is developed with a gate electrode layer comprising multiple sections of varying diameters, formed through precise etching and deposition processes, which surrounds the nanosheet channels, and includes a cladding layer with a controlled thickness to minimize germanium loss and optimize gate electrode formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor dimensions are scaled down to increase device density, then production efficiency and cost are improved, but gate control and short-channel effects deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional nanosheet channels with gate-all-around configuration. The gate electrode completely surrounds the nanosheet channel in three dimensions, providing superior electrostatic control over the channel region. This dimensional change enables effective gate control at scaled dimensions by utilizing the third dimension for gate wrapping, thereby suppressing short-channel effects while maintaining high device density.
2Reliability
If nanosheet FET structure is implemented to improve gate control, then device performance is enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary patterning actions where sacrificial layers are first formed to define the nanosheet channel regions before gate electrode deposition. The sacrificial layers are strategically placed and removed in advance to create the desired nanosheet structure, enabling subsequent gate-all-around formation without requiring complex in-situ shaping operations. This preliminary structuring simplifies the overall manufacturing sequence.
Solution Approach 2:
The patent uses sacrificial layers as intermediary materials that facilitate the formation of the nanosheet channel structure. These temporary structures serve as placeholders and etch stop layers during the fabrication process, enabling precise definition of the nanosheet regions. The sacrificial layers are removed after serving their structural definition purpose, leaving the desired nanosheet configuration without requiring direct complex patterning of the channel material itself.
3Loss of substance
If cladding layer thickness is reduced to minimize germanium loss, then material efficiency is improved, but gate electrode formation precision becomes more difficult
Solution Approach 1:
The patent optimizes the cladding layer thickness parameter to a specific range that balances germanium loss prevention with manufacturability. By carefully controlling the cladding layer thickness parameter, the process achieves minimal germanium loss during etching while maintaining sufficient structural integrity for subsequent gate electrode formation. This parameter optimization resolves the trade-off between material efficiency and manufacturing precision.
Solution Approach 2:
The patent applies different material compositions and thicknesses to different regions of the structure. The cladding layer has specific local properties optimized for protecting the nanosheet channel during fabrication, while the gate electrode region has different properties optimized for electrical performance. This local differentiation allows the cladding layer to be thin enough to minimize germanium loss yet provide sufficient protection and structural support where needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure enhances gate control and reduces manufacturing costs by maintaining device performance and minimizing short-channel effects, while also preventing germanium loss during the fabrication process.
Implementation Method 1
a nitrogen-containing oxidizing blocking layer... to minimize germanium loss and improve the manufacturing process
Implementation Method 2
annealing the high-k dielectric layer at a reduced temperature... prevents underetching during the formation of nanosheet channels
Data Source
AI summary
A semiconductor device structure is provided. The device includes a plurality of semiconductor layers vertically stacked, and a gate electrode layer comprising an upper portion disposed between two adjacent gate spacers, the upper portion having a first diameter. The gate electrode layer also includes a lower portion disposed below the upper portion including a first part surrounding each semiconductor layer of the plurality of semiconductor layers and a second part adjacent the first part, the second part comprising a first section having a second diameter that is less than the first diameter, a second section below the first section, the second section having a third diameter different than the second diameter, and a third section below the second section, wherein the third section has a fourth diameter different than the second diameter and the third diameter, wherein the first and second parts are formed as an integral.