Variable-Thickness Dielectric Layers for Scaled MOSFET Performance
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Solution Overview
Problem
As semiconductor devices are scaled down, the operating characteristics of MOSFETs deteriorate, necessitating improved methods for fabricating devices with superior performance while overcoming integration limitations.
Innovation Solution
A semiconductor device design featuring a substrate with distinct regions, including a peripheral region and logic cell region, where channel patterns and gate electrodes are stacked vertically, with varying thicknesses and widths of dielectric layers to enhance electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOSFET sizes are scaled down to increase integration, then device density increases, but operating characteristics deteriorate
Solution Approach 1:
The patent applies different dielectric layer configurations to different regions: the peripheral region uses a first dielectric layer with first thickness, while the logic cell region uses a second dielectric layer with second thickness. This local differentiation allows optimization of electrical characteristics for each region's specific functional requirements while maintaining high integration density across the entire device.
Solution Approach 2:
The invention changes the thickness parameter of the dielectric layer between the channel and gate electrode based on region: a first thickness for peripheral region transistors and a second thickness for logic cell region transistors. This parameter variation enables tailored electrical performance optimization for different functional blocks within the same integrated circuit.
2Reliability
If gate electrode thickness is increased to improve electrical characteristics, then transistor performance improves, but device area increases
Solution Approach 1:
Different gate electrode thicknesses are applied to different regions: the peripheral region uses a first gate electrode thickness while the logic cell region uses a second gate electrode thickness. This allows each region to have optimized electrical characteristics appropriate to its function without unnecessarily increasing the area of regions that don't require thicker gates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves electrical performance by optimizing gate electrode thickness and dielectric layer thickness, enhancing the operational efficiency of transistors in both regions.
Implementation Method 1
a first high-k dielectric layer between the first gate electrode and the first channel pattern
Implementation Method 2
a first interface dielectric layer between the first high-k dielectric layer and the first channel pattern
Data Source
AI summary
Disclosed is a semiconductor device comprising a substrate including a peripheral region and a logic cell region, a first channel pattern including a first and a second semiconductor pattern stacked vertically on the peripheral region, a first gate electrode across the first channel pattern and extending in a first direction, a second channel pattern including a third and a fourth semiconductor pattern stacked vertically on the logic cell region, and a second gate electrode across the second channel pattern and extending in the first direction, the second gate electrode having a second width in a second direction less than a first width in the second direction of the first gate electrode. The first gate electrode has a first thickness between the first and the second semiconductor pattern, and the second gate electrode has a second thickness between the third and the fourth semiconductor pattern greater than the first thickness.