Variable Entry Ring Storage for GPU State Cache Latency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Modern GPUs face performance issues due to slow access times in state caches, particularly in tile-based deferred rendering architectures, where repeated draw calls increase data access latency and hinder overall GPU performance.
Innovation Solution
Implementing a variable entry transitional ring storage system that allows efficient storage and reuse of graphics states across multiple draw calls, utilizing a circular buffer architecture to minimize state cache access latency and optimize buffer space utilization by reusing states and preloading future states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is fetched from state cache and stored in internal buffer before computation, then data access is organized and computations can proceed, but access latency is exposed and GPU performance is reduced
Solution Approach 1:
The system pre-fetches state data from the state cache into the internal buffer before it is actually needed for computation. By anticipating future data needs and loading them in advance, the system hides the cache access latency behind the buffer, allowing computations to proceed without waiting for slow cache accesses.
Solution Approach 2:
The internal buffer acts as an intermediary layer between the slow state cache and the computation units. Instead of directly accessing the cache during computation, the system uses the buffer as a middle ground that can be quickly accessed, thereby masking the latency of the underlying cache.
2Productivity
If draw calls are repeated for primitives in TBDR architecture, then rendering is completed, but data access to state variables increases multifold with little temporal locality
Solution Approach 1:
Instead of repeatedly accessing the state cache for each repeated draw call, the system loads state data once into the internal buffer and reuses this copied data across multiple draw calls. This eliminates redundant cache accesses and significantly reduces the total volume of data accessed while maintaining rendering productivity.
3Ease of operation
If state cache access latency is exposed in GPU pipeline, then subsequent work can be dependent on state variable data, but overall GPU performance is significantly hurt
Solution Approach 1:
The system performs preliminary data loading into the internal buffer before the GPU pipeline needs to access the state variables. This ensures that when subsequent work in the pipeline depends on this data, it is already available in the fast buffer rather than waiting for slow cache access, thus maintaining both pipeline dependency and high GPU performance.
Data Source
AI summary
A method includes determining that a new draw call is received; comparing a state identity (ID) of a graphics state stored in the ring storage with a state ID of a graphics state associated with the new draw call; determining if the ring storage has available space to store the graphics state associated with the new draw call; storing the graphics state associated with the new draw call in the ring storage, based on determining that the ring storage has available space; determining a location of a first valid and non-default entry and a last valid and non-default entry of the graphics state associated with the new draw call stored in the ring storage; and collecting data from one or more valid entries of the graphics state associated with the new draw call stored in the ring storage to complete a task associated with the new draw call.