Variable Fin Pitch Vertical-Transport FinFET
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Solution Overview
Problem
Vertical-transport FinFETs face a limitation in effective channel width due to their architecture, which restricts current flow and increases resistance between source and drain, making it challenging to achieve high drive strength while maintaining compatibility with existing circuit designs.
Innovation Solution
A vertical-transport FinFET device with a locally-variable fin pitch is developed, where source, drain, and channel regions are merged to form a consolidated architecture, allowing for a tighter fin pitch and improved drive strength and capacitance, benefiting logic circuit density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the fin dimension is increased to provide additional channel cross section, then the effective channel width is improved, but the distance between source and drain increases which increases resistance
Solution Approach 1:
The patent transitions from planar FinFET architecture to vertical-transport FinFET architecture, changing the current flow direction from lateral to vertical. This dimensional change allows the channel to extend vertically above the substrate surface, providing additional channel cross-section area without increasing the lateral distance between source and drain contacts, thereby improving effective channel width while maintaining low resistance
Solution Approach 2:
The patent employs merged source/drain regions that combine multiple fin structures into a consolidated architecture. This composite structure allows multiple fins to share common source and drain regions, effectively increasing the total channel width while maintaining compact spacing and minimizing resistance between source and drain
2Power
If multiple fins are arranged in parallel to provide higher drive strength, then the current flow capability is improved, but the device area increases which reduces circuit density
Solution Approach 1:
The patent merges adjacent fins into a consolidated vertical structure where multiple fins share common source and drain regions. This merging approach increases the effective channel width and drive strength without requiring proportional increases in device area, as the shared source/drain regions eliminate redundant structures and reduce overall footprint
Solution Approach 2:
By arranging fins vertically rather than laterally, the patent packs multiple channel structures into a smaller lateral footprint. The vertical stacking allows higher fin density within the same device area, increasing drive strength while maintaining or improving circuit density
3Area of stationary object
If a tighter fin pitch is implemented to improve logic circuit density, then the device density is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary patterning steps where mandrels are formed first, followed by spacer deposition that self-aligns to define the fin positions. This preliminary structuring establishes a framework that guides subsequent processing steps, enabling tight fin pitch implementation through self-aligned processes that reduce variability and simplify manufacturing control
Solution Approach 2:
The patent utilizes self-aligned spacer formation where spacers automatically position themselves relative to mandrels through conformal deposition. This self-service mechanism eliminates the need for additional alignment steps and lithography processes, enabling tight fin pitch implementation without proportionally increasing manufacturing complexity
Data Source
AI summary
A semiconductor device includes a plurality of vertical-transport fin field effect transistors that are arranged at a locally-variable fin pitch. Within a first region of the device, a first plurality of fins are arranged at a first pitch (d1), and within a second region of the device, a second plurality of fins are arranged as a second pitch (d2) less than the first pitch. The second plurality of fins share merged source, drain and gate regions, while the source, drain and gate regions for the first plurality of fins are unmerged.