Variable Frame Rate Video Display Using Dual Timing Control Buffers
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Solution Overview
Problem
Current systems fail to directly display variable frame rate digital video content without causing visual artifacts due to frame rate changes, with existing solutions either introducing noticeable dummy frames or requiring additional processors that can alter the original content.
Innovation Solution
A video display system that uses a first and second timing control buffer to store parameters for current and future frame rates, allowing instantaneous switching to the new frame rate upon detection of a frame rate boundary, with ancillary data embedded in the digital video stream to manage the frame rate changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If variable frame rate video content is displayed using conventional systems, then the display system can handle different frame rates, but visual artifacts appear due to the time required for the display device to synchronize to the new frame rate
Solution Approach 1:
The patent applies preliminary action by pre-loading timing control buffer parameters for future frame rates before they are needed. When a frame rate change is detected in the incoming video stream, the display system already has the necessary timing parameters ready in the buffer, allowing instantaneous switching without synchronization delays that cause visual artifacts.
Solution Approach 2:
The timing control buffer acts as an intermediary between the video input and display hardware. It stores and manages timing parameters for different frame rates, mediating the transition between frame rate changes and eliminating the direct synchronization conflict that causes visual artifacts in conventional systems.
2Object-affected harmful factors
If dummy or black frames are inserted to mask artifacts, then visual artifacts become less visible, but the dummy frames may be noticed by the viewer
Solution Approach 1:
The patent converts the potentially harmful frame rate transition artifacts into a benefit by using the timing control buffer to predict and prepare for frame rate changes. Instead of masking artifacts with dummy frames, the system proactively manages the transition timing to prevent artifacts from occurring in the first place, thereby preserving video content integrity.
3Stability of the object's composition
If an additional processor is employed to convert variable frame rate data into single frame rate data, then frame rate consistency is achieved, but the original content may be altered through interpolation
Solution Approach 1:
The patent segments the timing control functionality into a separate buffer structure that handles frame rate management independently from the video data processing. This allows the display system to maintain variable frame rate consistency without requiring additional processors that would alter the original video content through interpolation.
Solution Approach 2:
The timing control buffer serves itself by automatically detecting frame rate changes in the incoming video stream and managing the timing parameters without requiring external processing. This self-service mechanism maintains frame rate consistency while preserving the original video content fidelity.
4Reliability
If the display system takes time to synchronize to a new frame rate, then the system can properly comprehend the new rate, but visual artifacts occur during the synchronization period
Solution Approach 1:
The system performs preliminary action by pre-loading and storing timing control buffer parameters for anticipated frame rate changes. This preparation eliminates the synchronization delay by having the correct timing parameters ready before the frame rate transition occurs, allowing instantaneous and accurate frame rate switching without visual artifacts.
Data Source
AI summary
Methods are described for displaying video including variable frame rates. A method for displaying images includes receiving digital video data including video image data in a display system capable of displaying images at multiple frame rates; storing the digital video data in at least one frame buffer coupled to the display system; receiving in the digital video data ancillary data comprising at least configuration parameters indicating a current frame rate and a future frame rate; storing the parameters representative of a current frame rate in a first timing control buffer coupled to the display system; storing the parameters representative of a future frame rate in a second timing control buffer; displaying images from data in the frame buffer at the current frame rate; and upon detection of a swap condition, instantly displaying images from data in the frame buffer at the future frame rate. Additional methods and apparatus are described.