Variable Frequency Clock Circuit for Stepping Motor Synchronization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing variable frequency clock output circuits for image forming apparatuses are complex and lack versatility, making it difficult to accurately accelerate or decelerate stepping motors to various target frequencies, which is essential for maintaining synchronization and improving productivity and image quality.
Innovation Solution
A variable frequency clock output circuit with a target value register, an increase/decrease value register, an adder-subtractor, a comparator, and a clock generator, which allows for precise adjustment of motor frequencies by comparing the output value to the target value and generating a clock signal proportional to the calculated result, enabling smooth acceleration or deceleration to different target frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software processing using CPUs and memories is used to generate variable frequency clocks, then frequency adjustment capability is achieved, but device complexity and software control load increase
Solution Approach 1:
The patent replaces software-based frequency control with a hardware-based variable frequency clock output circuit. The circuit uses hardware components (registers, adders, comparators, counters) to directly generate variable frequency clocks, eliminating the need for CPU software processing and complex control programs.
Solution Approach 2:
The variable frequency clock output circuit is designed to autonomously generate variable frequency clocks based on preset parameters stored in registers. The circuit automatically performs frequency calculation, comparison, and clock generation without requiring external CPU intervention or software control, reducing the software control load.
2Device complexity
If a fixed-structure clock output circuit is used, then device simplicity is maintained, but versatility in adjusting to various target frequencies is limited
Solution Approach 1:
The patent introduces dynamic parameters (target frequency, acceleration/deceleration rate) that can be preset in registers and changed during operation. The circuit dynamically adjusts the clock frequency based on these parameters, allowing it to adapt to various target frequencies while maintaining a relatively simple hardware structure.
Solution Approach 2:
The circuit allows changing of key parameters (target frequency Ftarget, acceleration/deceleration rate a) to adapt to different operating conditions. By modifying these parameters in the registers, the same circuit structure can achieve versatile frequency adjustment without requiring structural changes.
3Productivity
If frequency change rate is increased to improve productivity, then paper conveyance speed increases, but loss of synchronism between control clock and motor revolution occurs
Solution Approach 1:
The patent implements periodic acceleration and deceleration phases in the frequency change process. The circuit uses preset acceleration/deceleration rates to smoothly transition between frequencies, preventing abrupt changes that would cause synchronization loss. This periodic adjustment pattern maintains motor-synchronization while improving overall conveyance speed.
Solution Approach 2:
The circuit preset acceleration/deceleration parameters and target frequencies in registers before operation. By pre-calculating and storing the optimal frequency transition parameters, the circuit can execute smooth frequency changes that maintain synchronization, avoiding the need for real-time complex calculations that would delay the response.
4Productivity
If multiple stepping motors are accelerated to different target frequencies, then productivity and image quality improve, but control complexity increases
Solution Approach 1:
The patent designs a universal variable frequency clock output circuit that can control multiple stepping motors with different requirements. The circuit accepts different parameter sets (target frequency, acceleration rate) for each motor channel, allowing independent control of multiple motors while using the same basic circuit architecture, thus avoiding the need for separate control systems for each motor.
Data Source
AI summary
A variable frequency clock output circuit, comprising: a target value register which stores a target value corresponding to an arbitrarily set target frequency; an increase/decrease value register which stores an arbitrarily set increase/decrease value; an adder-subtractor which has an input portion into which a current output value is inputted and outputs a calculation result obtained by adding/subtracting the increase/decrease value stored in the increase/decrease value register to/from the current output value inputted into the input portion based on an addition/subtraction instruction signal; a comparator which compares an output value of the adder-subtractor to the target value stored in the target value register, and outputs an addition/subtraction instruction signal to the adder-subtractor until the output value of the adder-subtractor and the target value coincide; and a clock generator which outputs a clock signal having a frequency proportional to the output value of the adder-subtractor.