Variable Frequency Signal Synthesizer Without PLL Mismatch Calibration
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Solution Overview
Problem
Conventional variable frequency signal synthesizers face limitations in modulation bandwidth, suffer from gain and timing mismatches, and have high power consumption and large die size due to complex structures, restricting feasible modulation depth and period.
Innovation Solution
A variable frequency signal synthesizer incorporating a phase locked loop with a time-to-digital converter, digital loop filter, digitally controlled oscillator, and frequency slope tracker, which generates a frequency control signal by accumulating phase and frequency differences, preventing gain and timing mismatches while maintaining low power consumption and small die size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a two-point modulation scheme is used to achieve wider modulation bandwidth, then modulation bandwidth is improved, but gain mismatch and timing mismatch occur requiring complex calibration circuits
Solution Approach 1:
The patent extracts and eliminates the calibration circuit from the two-point modulation scheme by transitioning to a one-point modulation scheme where the modulated signal is supplied only to the delta sigma modulator in the PLL, removing the source of gain and timing mismatches while maintaining wide modulation bandwidth through digital frequency control
Solution Approach 2:
The patent changes the modulation scheme from two-point to one-point modulation, fundamentally altering how frequency modulation is achieved by supplying the modulated signal exclusively to the delta sigma modulator rather than to both the VCXO/VCO and delta sigma modulator, thereby eliminating mismatch issues
2Measurement precision
If a calibration circuit is included to compensate gain mismatch and timing mismatch, then matching precision is improved, but device complexity and die size increase
Solution Approach 1:
The patent removes the calibration circuit entirely by adopting a one-point modulation scheme, eliminating the need for gain and timing mismatch compensation hardware and thereby reducing die size while maintaining signal synthesis functionality
Solution Approach 2:
The patent uses digital frequency control through the delta sigma modulator to replicate the frequency control function that would otherwise require analog calibration circuits, achieving precise frequency control without additional hardware
3Measurement precision
If a calibration circuit is included to compensate gain mismatch and timing mismatch, then matching precision is improved, but power consumption increases
Solution Approach 1:
The patent eliminates the calibration circuit by transitioning to one-point modulation, removing the power-consuming components dedicated to gain and timing mismatch compensation while maintaining frequency control precision through digital means
4Stability of the object's composition
If conventional synthesis methods are used, then frequency stability is maintained, but modulation depth is limited to several thousand ppm
Solution Approach 1:
The patent changes the modulation implementation from analog VCXO/VCO modulation to digital delta sigma modulation, enabling much larger modulation depths (exceeding several thousand ppm) while maintaining frequency stability through the PLL's feedback control mechanism
5Speed
If conventional synthesis methods are used, then frequency control is achieved, but modulation period is relatively long at several milliseconds
Solution Approach 1:
The patent replaces the analog mechanical-style frequency control (through VCXO/VCO) with digital frequency control through the delta sigma modulator and PLL, enabling much faster frequency changes with modulation periods reduced from milliseconds to microseconds or less
Data Source
AI summary
A variable frequency signal synthesizer includes a phase locked loop including a time-to-digital converter configured to detect differences in phase and frequency between a reference signal and a feedback clock signal and output error signals corresponding to the detected differences, a digital loop filter, a digitally controlled oscillator, and a first frequency divider configured to divide output signals of the digitally controlled oscillator at a predetermined frequency division ratio, a feedback clock generation unit configured to generate sign signals and a phase-modulated feedback clock signal, and a frequency slope tracker configured to generate a frequency control signal by accumulating differences in the error signals according to signs corresponding to the sign signals. The digitally controlled oscillator receives the frequency control signal to supply an output variable frequency signal.