Variable Frequency Write Pattern Generation in HDD Read/Write Units
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Solution Overview
Problem
Current hard disk drive (HDD) systems face challenges in rapidly changing frequency patterns during read/write operations, which can lead to delays and suboptimal bit error rates (BER) due to the settling time of phase-locked loops (PLLs), limiting data density uniformity across the disk.
Innovation Solution
The implementation of a system comprising phase-locked loops (PLLs), an interpolator unit, a delay-locked loop, and a precompensation unit that generates timing signals with fast frequency changes by interpolating and delaying clock signals, applying precompensation to achieve variable frequency patterns without incurring delay, thereby optimizing BER and data density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a phase-locked loop (PLL) based time base generator is used to generate clock signals, then frequency stability is improved, but frequency changing speed deteriorates due to settling time
Solution Approach 1:
The system pre-calculates and stores frequency adjustment values in a lookup table before they are needed. When frequency change is required, the pre-computed values are immediately applied without waiting for PLL settling, thus achieving fast frequency switching while maintaining stability through the stored calibrated values
Solution Approach 2:
The frequency adjustment process is segmented into discrete steps with specific adjustment values stored in a lookup table. Instead of continuous analog adjustment, the system uses segmented digital steps that can be rapidly switched without settling time, resolving the contradiction between stability and switching speed
2Reliability
If frequency is changed at each servo wedge to optimize bit error rate and data density, then data quality is improved, but time delay increases due to PLL settling time
Solution Approach 1:
Frequency adjustment values are pre-calculated and stored in a lookup table corresponding to different servo wedge positions. When the head moves to a new servo wedge, the corresponding pre-computed frequency adjustment is immediately retrieved and applied, eliminating the time delay that would otherwise be required for PLL settling while still achieving the optimal bit error rate for each position
Solution Approach 2:
The system replaces the mechanical/analog PLL frequency adjustment mechanism with a digital lookup table-based approach. Instead of relying on the physical settling process of the PLL, the system uses digital memory retrieval and application of pre-computed values, substituting a fast electronic process for a slower mechanical/analog process
3Stability of the object's composition
If constant angular velocity is used for disk rotation, then rotation stability is improved, but data density uniformity deteriorates across different radial zones
Solution Approach 1:
The system applies dynamic frequency adjustment based on the radial position of the read/write head. Instead of using a fixed constant angular velocity approach, the system dynamically changes the data clock frequency according to the servo wedge position, allowing the effective linear velocity at the head to be optimized for each radial zone while the disk itself rotates at constant angular velocity, thus achieving uniform data density across all zones
Data Source
AI summary
In some implementations, a system includes a magnetic media disk and a read/write unit. The read/write unit includes a plurality of phase-locked loops (PLLs), an interpolator unit, a delay-locked loop, and a precompensation unit. The PLLs are configured to generate, using a reference clock signal, a first plurality of clock signals having different frequencies phases. The interpolator unit is configured to interpolate the first plurality of clock signals in accordance with a frequency offset signal to generate a single-phase clock signal. The delay-locked loop is configured to delay the single-phase clock signal in accordance with a PLL data clock signal to generate a second plurality of clock signals having different phases. The precompensation unit is configured to apply precompensation to the second plurality of clock signals to generate a timing signal for writing data to the magnetic media disk.