Multigate GAA Transistors with Variable Nanostructures for IC Fabrication
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing GAA devices face challenges in integrating different channel configurations for varying performance and circuit applications, complicating IC manufacturing processes.
Innovation Solution
A method for fabricating GAA transistors with different channel configurations by varying the number of nanostructures on a substrate, allowing for high-performance or low-power applications through precise control of channel regions and source/drain configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different channel configurations are integrated into IC manufacturing processes, then device performance and circuit application versatility are improved, but manufacturing process complexity increases
Solution Approach 1:
The manufacturing process is segmented into distinct stages: forming sacrificial layers with specific patterns, depositing gate materials, and selectively removing sacrificial layers. This segmentation allows different channel configurations to be created through controlled removal of specific sacrificial layers, enabling versatility while maintaining manageable process complexity through modular fabrication steps
Solution Approach 2:
Sacrificial layers are pre-formed with specific patterns and configurations before the gate structure is deposited. These preliminary sacrificial structures serve as templates that define the final channel configurations. By preparing these templates in advance, the process achieves high adaptability to different channel designs without complicating the subsequent gate formation steps
2Productivity
If conventional IC manufacturing processes are used, then manufacturing cost and production efficiency are improved, but gate control and short-channel effects are degraded
Solution Approach 1:
The gate structure is designed to provide different degrees of wrap-around control at different locations along the channel. By varying the gate configuration locally (e.g., partial vs. full wrap-around), the device achieves improved gate control and reduced short-channel effects in specific regions while maintaining compatibility with conventional manufacturing processes that can produce these varied local structures
Solution Approach 2:
The gate structure transitions from conventional planar 2D configuration to a 3D wrap-around structure that extends vertically and laterally around the channel. This dimensional change provides enhanced gate control and electrostatic control over the channel, improving reliability by reducing short-channel effects while still being fabricable using extended conventional processes
Data Source
AI summary
Methods include providing a first fin structure and a second fin structure each extending from a substrate. A first gate-all-around (GAA) transistor is formed on the first fin structure; the first GAA transistor has a channel region within a first plurality of nanostructures. A second GAA transistor is formed on the second fin structure; the second GAA transistor has a second channel region configuration. The second GAA transistor has a channel region within a second plurality of nanostructures. The second plurality of nanostructures is less than the first plurality of nanostructures.