Variable-Gain PLL Loop Filter for Fast Lock and Low Jitter
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Solution Overview
Problem
Existing phase locked loop (PLL) circuits face challenges in reducing the lock time required to stabilize a clock signal, particularly as clock frequencies increase and noise such as jitter becomes more significant.
Innovation Solution
A phase locked loop circuit that includes a phase-frequency detection circuit, a lock detection circuit, a charge pump circuit, a loop filter, and an oscillator. The circuit adjusts the phase gain based on the phase difference between the reference and feedback clock signals, generates control signals to precharge and discharge a loop filter output node, and adjusts the loop filter impedance based on a lock detection signal to optimize filtering performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the gain of the phase-frequency detector is increased to reduce in-band noise, then noise reduction is improved, but the lock time increases
Solution Approach 1:
The patent applies dynamics by making the phase-frequency detector gain variable rather than fixed. The gain is dynamically adjusted based on the lock status: a first gain value is used during the acquisition phase to enable fast locking, and a second gain value (different from the first) is used during the tracking phase to minimize in-band noise. This dynamic gain adjustment resolves the contradiction between fast lock time and noise reduction.
Solution Approach 2:
The patent changes the parameter of phase-frequency detector gain based on operational phase. The control circuit modifies the gain parameter transition from a first gain value to a second gain value when lock is detected, allowing the system to optimize performance for different operational requirements (acquisition speed vs. noise performance) at different times.
2Object-affected harmful factors
If the loop filter impedance is adjusted to optimize filtering performance, then noise reduction is improved, but the circuit complexity increases
Solution Approach 1:
The patent applies dynamics by making the loop filter impedance variable. The impedance is dynamically adjusted based on lock status: a first impedance value is used during acquisition, and a second impedance value is used during tracking. This allows the loop filter to optimize noise reduction performance during tracking while maintaining stable operation during acquisition, without requiring multiple complex filter circuits.
Solution Approach 2:
The patent makes a single loop filter circuit perform multiple functions by changing its impedance characteristic. The same loop filter circuit serves both acquisition and tracking phases with different impedance values, eliminating the need for separate filter circuits for each phase and thus avoiding increased circuit complexity.
3Speed
If the phase gain is adjusted dynamically to reduce lock time, then stabilization speed is improved, but the control circuit complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-setting two distinct gain values for the phase-frequency detector. The control circuit is designed to switch between these predetermined gain values based on lock detection, avoiding the need for complex real-time gain calculation circuits. The gain values are prepared in advance for different operational phases.
Solution Approach 2:
The patent changes the phase gain parameter based on lock status to achieve fast stabilization. The control circuit adjusts the gain from a first value to a second value when lock is detected, allowing rapid transition from acquisition to tracking mode without requiring complex adaptive algorithms.
Data Source
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AI summary
There is provided a phase locked loop circuit (1) including a phase-frequency detection circuit (100) configured to receive a reference clock signal (REF_CK) and a feedback clock signal (FEED_CK) having a phase difference from each other, adjust a phase gain based on phase difference, and generate first and second control signals (UP, DN) based on the phase gain, a lock detection circuit (110) configured to generate a lock detection signal (LDS) based on the phase difference, a charge pump circuit (200) configured to generate a loop filter input signal (LFin) based on the first and second control signals (UP, DN), a loop filter (300) configured to adjust impedance (ZLF) based on the activated lock detection signal (LDS) and generate a loop filter output signal (LFout) based on the adjusted impedance (ZLF), an oscillator (400) configured to generate a clock signal (CK) based on the loop filter output signal (LFout), and a divider (500) configured to generate the feedback clock signal (FEED _CK) by dividing the clock signal (CK).