Variable Gain Amplifier Resistance Network With Fewer Switches
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Solution Overview
Problem
Conventional variable gain amplifier circuits require a large number of switches to achieve desired resistance values, making it difficult to set the combined resistance circuit to specific values in both parallel and series configurations.
Innovation Solution
A combined resistance circuit design that uses a specific configuration of resistors and switches, where the resistance ratios between certain resistors are equal, allowing for a small number of switches to achieve multiple desirable resistance values, thereby reducing the number of switches needed and minimizing parasitic capacitance effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a large number of switches are used in parallel or series configuration to achieve desired resistance values, then the resistance value precision is improved, but the device complexity and parasitic capacitance increase
Solution Approach 1:
The circuit is divided into multiple bridge circuits (first bridge circuit with switches SW0-SW3, second bridge circuit with switches SW4-SW7) that can be independently controlled. Each bridge circuit segment contributes to the overall resistance value, allowing precise resistance control through coordinated switching of multiple segments rather than using a single large switch network
Solution Approach 2:
The patent transitions from traditional single-dimension switch networks to a two-dimensional bridge circuit topology. The bridge configuration allows resistance control through both series and parallel combinations within each bridge, creating a multi-dimensional resistance adjustment space that achieves higher precision with fewer total switches
2Manufacturing precision
If many constituent units are connected in parallel or series to achieve desired resistance values, then the resistance value precision is improved, but the layout area increases
Solution Approach 1:
The circuit is divided into multiple bridge circuits (first bridge circuit with switches SW0-SW3, second bridge circuit with switches SW4-SW7) that can be independently controlled. Each bridge circuit segment contributes to the overall resistance value, allowing precise resistance control through coordinated switching of multiple segments rather than using a single large switch network
Solution Approach 2:
Multiple bridge circuits are merged in a parallel configuration where each bridge contributes to the overall resistance control. The first and second bridge circuits share common nodes and can be controlled cooperatively, reducing the total layout area compared to separate resistance control circuits while maintaining precision through the combined switching action of all bridges
3Adaptability or versatility
If a large number of switches are used in the combined resistance circuit, then the adaptability for achieving various resistance values is improved, but the parasitic capacitance effects increase
Solution Approach 1:
The circuit is divided into multiple bridge circuits (first bridge circuit with switches SW0-SW3, second bridge circuit with switches SW4-SW7) that can be independently controlled. Each bridge circuit segment contributes to the overall resistance value, allowing precise resistance control through coordinated switching of multiple segments rather than using a single large switch network
Solution Approach 2:
The patent achieves wide resistance value range and high precision by dynamically changing the state (on/off) of multiple switches in coordinated patterns. The control signals S0-S7 independently control each switch, enabling the circuit to transition between numerous resistance states through parameter changes in switch configurations rather than physically changing the circuit topology
Data Source
AI summary
A combined resistance circuit 2A includes a first circuitry 20A provided between a first end 2a and a second end 2b. This first circuitry 20A includes a resistor R1 provided between a node N11 and a node N12, a resistor R2 provided between the node N12 and a node N13, a resistor R3 provided between the node N13 and a node N14, a resistor R4 provided between the node N14 and the node N11, a resistor R5 provided between the node N11 and the node N13, a switch SW0 provided in series to the resistor R4 between the node N14 and the node N11, and a switch SW1 provided in series to the resistor R2 between the node N12 and the node N13. The node N12 is connected to the first end and the node N14 is connected to the second end.


