Variable-Width Gate Cut Pattern for Scaled MBCFET Integration
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Solution Overview
Problem
As semiconductor devices are scaled down, the challenge of maintaining efficient transistor performance and integration density is exacerbated by the need for precise and scalable gate electrode and cutting pattern designs.
Innovation Solution
A semiconductor device is designed with a substrate featuring distinct active regions, gate electrodes, and cutting patterns that vary in width and configuration to optimize transistor performance and integration, including a three-dimensional field effect transistor (MBCFET) structure with specific gate dielectric layers and metal layers for enhanced connectivity and separation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the gate electrode width is reduced to scale down transistor sizes, then integration density is improved, but manufacturing precision requirements worsen
Solution Approach 1:
The cutting pattern is designed with non-uniform width: wider at the first end (adjacent to first gate electrode) and narrower at the second end (adjacent to second gate electrode). This local variation in geometry allows the single cutting pattern to accommodate two different gate electrode widths, enabling scaled-down transistor sizes while maintaining appropriate manufacturing tolerances for each region.
2Reliability
If the cutting pattern width is increased to ensure complete penetration, then reliability is improved, but area occupied worsens
Solution Approach 1:
The cutting pattern employs variable width along its length: the first end has greater width to ensure reliable penetration and separation of the first gate electrode, while the second end has reduced width to minimize area occupation. This local differentiation optimizes both penetration reliability and space efficiency.
Solution Approach 2:
The cutting pattern is designed with asymmetric geometry where the width varies from one end to the other. The first end is wider than the second end, creating an asymmetric shape that tailors the penetration capability to the specific requirements of each gate electrode region while minimizing overall area.
Data Source
AI summary
A semiconductor device including a substrate that includes first and second regions; a first active pattern on the first region and a second active pattern on the second region; a first gate electrode on the first active pattern and a second gate electrode on the second active pattern; and a first cutting pattern that penetrates the first gate electrode and a second cutting pattern that penetrates the second gate electrode, wherein a width of the first gate electrode as measured in one direction is less than a width of the second gate electrode, a maximum width of the first cutting pattern is greater than the width of the first gate electrode, and a minimum width of the second cutting pattern is less than the width of the second gate electrode.