Variable Gate Oxide MOSFET for RF RON/COFF Tradeoff
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Solution Overview
Problem
Current MOSFET transistors for RF signal switching applications face challenges in optimizing electric performance due to high parasitic capacitance in the off-state and increased on-state resistance, which affects their efficiency and performance across a wide range of frequencies.
Innovation Solution
The solution involves a MOSFET transistor design with a gate insulator layer that varies in thickness, having a thicker region near the edges and a thinner region near the center of the conductive gate, achieved through thermal oxidation, which reduces parasitic capacitance while maintaining low on-state resistance, thereby optimizing the RON/COFF tradeoff for RF signal switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If the gate insulator thickness is increased to reduce parasitic capacitance, then the off-state capacitance decreases, but the on-state resistance increases
Solution Approach 1:
The gate insulator is designed with non-uniform thickness: thinner (e.g., 2-5 nm) in the central region beneath the gate to minimize parasitic capacitance, and thicker (e.g., 5-10 nm) at the edges to prevent breakdown and control resistance. This spatial variation in thickness allows simultaneous optimization of both capacitance and resistance characteristics.
Solution Approach 2:
The gate insulator thickness parameter is varied continuously or stepwise across the device structure. By controlling the thickness gradient from center to edge, the patent achieves optimal balance between parasitic capacitance reduction and on-state resistance control, transforming a single-parameter design into a multi-parameter optimized structure.
2Reliability
If the gate insulator thickness is reduced to lower on-state resistance, then the on-state resistance decreases, but the parasitic capacitance increases
Solution Approach 1:
The gate insulator is designed with non-uniform thickness: thinner (e.g., 2-5 nm) in the central region beneath the gate to minimize parasitic capacitance, and thicker (e.g., 5-10 nm) at the edges to prevent breakdown and control resistance. This spatial variation in thickness allows simultaneous optimization of both capacitance and resistance characteristics.
Solution Approach 2:
The gate insulator thickness parameter is varied continuously or stepwise across the device structure. By controlling the thickness gradient from center to edge, the patent achieves optimal balance between parasitic capacitance reduction and on-state resistance control, transforming a single-parameter design into a multi-parameter optimized structure.
3Ease of manufacture
If the gate insulator thickness is made uniform, then the manufacturing process is simpler, but the RON/COFF tradeoff cannot be optimized
Solution Approach 1:
The gate insulator fabrication is segmented into multiple stages: first forming a base thickness layer, then selectively thickening edge regions through additional deposition or oxidation steps. This segmentation allows independent optimization of different regions while maintaining manufacturing feasibility through standardized process modules.
Solution Approach 2:
The gate insulator is designed with non-uniform thickness: thinner (e.g., 2-5 nm) in the central region beneath the gate to minimize parasitic capacitance, and thicker (e.g., 5-10 nm) at the edges to prevent breakdown and control resistance. This spatial variation in thickness allows simultaneous optimization of both capacitance and resistance characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively decreases parasitic capacitance in the off-state and maintains low on-state resistance, resulting in a favorable RON/COFF tradeoff, enhancing the transistor's performance for RF signal switching applications across frequencies from 3 kHz to 300 GHz.
Implementation Method 1
c) thermal oxidation of the gate insulator layer so that the gate insulator layer reaches a thickness e2 greater than e1 in front of the edges of the conductive gate
Data Source
AI summary
A transistor includes a semiconductor layer with a stack of a gate insulator and a conductive gate on the semiconductor layer. A thickness of the gate insulator is variable in a length direction of the transistor. The gate insulator includes a first region having a first thickness below a central region of the conductive gate. The gate insulator further includes a second region having a second thickness, greater than the first thickness, below an edge region of conductive gate.