Variable Gate Resistance for Semiconductor Switch Control
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Solution Overview
Problem
High gate resistance in semiconductor switches leads to increased switching losses and delay, limiting the efficiency and speed of semiconductor switch operation, especially in applications like photovoltaic inverters where a wide input voltage range is desired.
Innovation Solution
Implementing a method where a low-value gate turn-off resistance is used initially, transitioning to a higher-value resistance after current commutation begins, minimizing voltage peaking without significant increase in turn-off losses or switching delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a high gate resistance is used to limit voltage peaking during turn-off, then voltage peaking is reduced, but switching losses increase and switching speed decreases
Solution Approach 1:
The gate resistance is made dynamically variable rather than fixed. During the turn-off process, the resistance value changes from an initial high value to a final low value, allowing the system to adapt to different stages of the switching transient and resolve the contradiction between limiting voltage peaking and minimizing switching losses
Solution Approach 2:
The gate resistance parameter is changed during operation. The resistance value transitions from a first value (higher) to a second value (lower) based on the collector-emitter voltage threshold, enabling optimal performance at different stages of the turn-off process
2Object-affected harmful factors
If a high gate resistance is used to limit voltage peaking, then voltage peaking is reduced, but switching delay increases
Solution Approach 1:
The gate resistance is dynamically adjusted during the turn-off process, starting high to limit voltage peaking and then switching to low to reduce switching delay, thereby resolving the time-performance contradiction
Solution Approach 2:
The gate resistance changes in periodic stages corresponding to different phases of the turn-off transient, with the transition triggered when the collector-emitter voltage exceeds a threshold, enabling optimal control at different time intervals
3Speed
If a low gate resistance is used for fast switching, then switching speed is improved, but voltage peaking increases
Solution Approach 1:
A high gate resistance is applied initially during the early stage of turn-off to prevent voltage peaking before the current commutation is complete, and then switched to low resistance to enable fast switching in the later stage
Solution Approach 2:
The gate resistance is switched to a low value after the voltage peak is avoided, allowing the switching process to rush through the remaining phase quickly, thereby achieving fast switching without excessive voltage peaking
Data Source
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AI summary
A method and an arrangement for controlling a first semiconductor switch, which first semiconductor switch (S1) is connected in series with a second semiconductor switch (S2) between poles (udc+, udc-) of a DC voltage source, wherein the arrangement comprises means for turning the first semiconductor switch (S1) off by providing a control voltage, which turns the first semiconductor switch off, through a resistance (Roff1, Roff2) to the control electrode of the first semiconductor switch, the resistance (Roff1, Roff2) having a first value, when a voltage (uce,S2) between the input electrode and the output electrode of the second semiconductor switch (S2) is higher than a voltage threshold, and the resistance having a second value, when the voltage between the input electrode and the output electrode of the second semiconductor switch is lower than the voltage threshold, wherein the second resistance value is higher than the first resistance value.