Variable Gate Via Sizing for Bridging Risk and Resistance
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Solution Overview
Problem
As semiconductor device sizes shrink, electrical bridging between microelectronic components becomes a concern, leading to potential device failures and decreased functional density, as conventional designs attempt to prevent bridging by increasing spacing, which results in routing inefficiencies.
Innovation Solution
The implementation of gate vias and source/drain vias with varying sizes and locations, where the gate via with adjacent slot contacts has the smallest size to avoid bridging, the gate via without adjacent contacts has the largest size for reduced resistance, and the gate via with a single adjacent contact has an intermediate size, optimizing isolation and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If spacing among microelectronic components is increased to prevent electrical bridging, then reliability is improved, but functional density deteriorates
Solution Approach 1:
The patent applies local quality by configuring different via sizes at different locations within the same interconnect structure. Specifically, first vias adjacent to microelectronic components are made smaller than second vias not adjacent to components. This local differentiation allows smaller vias near components to reduce bridging risk while larger vias elsewhere maintain low resistance, thereby preventing electrical bridging without requiring increased spacing and preserving functional density.
2Reliability
If via size is reduced to prevent electrical bridging, then reliability is improved, but electrical resistance increases
Solution Approach 1:
The patent implements local quality by creating a spatially varying via size distribution where first vias adjacent to microelectronic components have a first size optimized for bridging prevention, while second vias not adjacent to components have a second size optimized for low resistance. This local differentiation resolves the contradiction by allowing each via to be sized according to its specific functional requirements rather than using a uniform size.
Solution Approach 2:
The patent applies segmentation by dividing the via population into distinct groups (first vias and second vias) with different size characteristics. First vias are segmented as smaller-diameter vias located adjacent to microelectronic components, while second vias are segmented as larger-diameter vias located away from components. This segmentation allows the system to simultaneously achieve bridging prevention and low resistance through differentiated via subsets.
Data Source
AI summary
A first gate structure, a second gate structure, and a third gate structure each extend in a first direction. A first gate via is disposed on the first gate structure. The first gate via has a first size. A second gate via is disposed on the second gate structure. The second gate via has a second size that is greater than the first size. A third gate via is disposed on the third gate structure. The third gate via has a third size that is less than the second size but greater than the first size. A first source contact is disposed adjacent to a first side of the first gate via. A first drain contact is disposed adjacent to a second side of the first gate via opposite the first side. A second drain contact is disposed adjacent to a first side of the third gate via.