Variable HBlank Timing Generator for Display Underflow
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Solution Overview
Problem
Graphics processing systems face performance degradation and visual defects due to contention for shared resources, leading to delays in accessing memory, which can result in the display of old data instead of current data.
Innovation Solution
Implementing a variable horizontal blanking interval by detecting a data ready signal to generate a line-transmit signal only when display data is available, ensuring that the display pipeline transmits data at the correct time, thus reducing display underflow and visual defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed horizontal blanking interval is used in the display pipeline, then the timing generator can operate with simple fixed timing, but display underflow occurs when data is not ready by the expected time, causing visual defects
Solution Approach 1:
The horizontal blanking interval is changed from a fixed value to a variable value that adapts based on data readiness. The timing generator dynamically adjusts the HBLANK duration using a variable counter that can extend the blanking period when data is delayed, thereby preventing display underflow while maintaining system reliability.
Solution Approach 2:
A data ready signal is introduced as feedback from the display pipeline to the timing generator. This signal informs the timing generator whether data is ready by the expected time, enabling the system to adjust the horizontal blanking interval dynamically based on actual data availability, thus resolving the contradiction between reliability and complexity.
2Reliability
If the display pipeline waits for data to be ready before transmitting, then visual defects are reduced, but contention delays in shared memory access worsen the timing issues
Solution Approach 1:
The system dynamically adjusts the horizontal blanking interval based on actual data readiness conditions. When contention delays cause data to be late, the variable HBLANK extends the timing window accordingly, allowing the display pipeline to maintain reliability without being constrained by fixed timing requirements.
Solution Approach 2:
The timing generator prepares and transmits the line-transmit signal only after confirming data readiness through the data ready signal. This preliminary verification action ensures that data is ready before transmission begins, preventing display underflow and visual defects even in the presence of contention delays.
3Adaptability or versatility
If multiple devices access shared memory concurrently, then system functionality is maintained, but contention delays cause the display pipeline to receive old data instead of current data
Solution Approach 1:
The data ready signal provides feedback to the timing generator about actual data availability. This feedback mechanism allows the system to accommodate concurrent memory access by adjusting timing based on when data is actually ready, ensuring that only current data is transmitted and preventing the display of old data.
Solution Approach 2:
The horizontal blanking interval becomes a dynamic parameter that adapts to memory access conditions. When contention causes delays in data availability, the variable HBLANK extends the timing window, allowing the system to maintain concurrent memory access while ensuring data freshness for display.
Data Source
AI summary
Methods and apparatus for improving the effects of display underflow using a variable horizontal blanking interval are disclosed. One embodiment of the present invention is a method of display that includes detecting a data ready signal that indicates availability of display data for transmission from a display pipeline, and generating a line-transmit signal based upon a clock signal and the data ready signal. The line-transmit signal is provided to the display pipeline. The line-transmit signal is substantially coincident with the clock signal if the data ready signal is set, and may be delayed if the data ready signal is not asserted. The display pipeline transmits the display data upon receiving the line-transmit signal. Another embodiment is an apparatus including a display pipeline configured to set a data ready signal when the display data is available for transmission, and a timing generator coupled to the display pipeline and configured to generate a line-transmit signal based on the status of the data ready signal.