Variable Height Conductive Bumps for BOT Reliability
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Solution Overview
Problem
The mismatch in thermal expansion coefficients between semiconductor chips and package substrates in Bump-on-Trace (BOT) structures leads to stress and peeling off of metal traces, especially with finer bump pitches, resulting in cold joints and reduced bonding force.
Innovation Solution
The semiconductor structure incorporates conductive bumps with adjustable heights over conductive traces on the substrate, where the height of the bumps is proportional to the minimum distance between the conductive pads and traces, ensuring secure electrical and mechanical connections without cold joints, using a design that varies bump heights between core and periphery regions based on substrate and chip alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If BOT structures are used to increase integration density, then chip area requirement is reduced, but metal traces peel off from package substrate due to CTE mismatch stress
Solution Approach 1:
The patent applies local quality by varying the height of conductive bumps based on their location. Bumps in the core region have different heights than bumps in the periphery region, allowing each region to be optimized for its specific stress conditions and functional requirements, thereby maintaining bonding integrity while achieving fine pitch integration
2Productivity
If finer bump pitches are used to increase integration density, then more components are integrated, but bonding force between conductive traces and package substrate decreases causing peeling
Solution Approach 1:
The patent changes the parameter of bump height to optimize bonding strength at fine pitches. By adjusting the height parameter of conductive bumps based on regional requirements, the invention maintains adequate bonding force between conductive traces and package substrate even when bump pitches are reduced to increase integration density
3Ease of manufacture
If uniform bump heights are used in BOT structures, then manufacturing is simplified, but cold joints occur due to substrate and chip alignment issues
Solution Approach 1:
The patent implements local quality by dividing the semiconductor chip into core and periphery regions with different bump height characteristics. This regional differentiation ensures that each bump achieves proper contact with its corresponding conductive trace despite variations in substrate and chip alignment, preventing cold joints while maintaining manufacturing feasibility
Data Source
AI summary
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate including a plurality of conductive traces and a recess filled with a conductive material electrically coupled to at least one of the plurality of conductive traces. The semiconductor structure also includes semiconductor chip. The semiconductor chip includes a plurality of conductive pads correspondingly electrically connected with the plurality of conductive traces through a plurality of conductive bumps. A height of each of the plurality of conductive bumps is determined by a minimum distance between the plurality of conductive pads and the corresponding conductive traces thereof.