Variable Height Cell Rows Using Extension Regions
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Solution Overview
Problem
Existing integrated circuit design methods are limited by the need to use standardized cell heights, which compromise between circuit performance, power consumption, and manufacturing efficiency, as they require cells to match a single cell height, restricting the ability to design smaller, faster, and more power-efficient circuits.
Innovation Solution
A system and method that allows for the placement of standard cells with different heights into a single cell row by using extension regions to connect cells of varying heights, enabling the choice of appropriately sized cells for desired efficiency and speed requirements without redesigning entire sections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single standardized cell height is used for all cells in a cell row, then manufacturing alignment and design rule compliance are improved, but circuit performance and power efficiency are worsened due to inability to select optimally sized cells
Solution Approach 1:
The cell row is segmented into multiple segments, each accommodating cells of different heights. Extension regions divide the cell row into first and second segments, allowing low threshold voltage cells (faster, higher power) and high threshold voltage cells (slower, lower power) to coexist in the same physical row without compromising alignment, thus resolving the contradiction between manufacturing precision and circuit performance
Solution Approach 2:
Different regions of the cell row are assigned different cell height characteristics. The first segment accommodates cells with first cell height while the second segment accommodates cells with second cell height (different from first height and not an integer multiple). This local differentiation allows optimal cell selection for specific circuit functions while maintaining overall manufacturing compliance
2Speed
If cells with low threshold voltage are used to improve circuit speed, then circuit performance is improved, but power consumption increases and additional masking steps are required during manufacturing
Solution Approach 1:
Low threshold voltage cells are placed locally in the first segment of the cell row where high speed is required, while high threshold voltage cells are placed in the second segment where lower power is acceptable. This spatial differentiation of cell characteristics allows the circuit to achieve high overall performance while managing power consumption strategically, rather than forcing all cells to use the same threshold voltage
Solution Approach 2:
The cell row is divided into segments that can accommodate different cell types with different threshold voltages. This segmentation allows the design to selectively use low threshold voltage cells (requiring extra masking) only where their high speed benefits are critical, while using standard cells elsewhere, thus optimizing the trade-off between speed and manufacturing complexity
3Device complexity
If the cell library is restricted to a single cell height to simplify design, then design complexity is reduced, but the ability to design smaller, faster, and more power-efficient circuits is limited
Solution Approach 1:
The cell row structure is designed to be universal, accommodating multiple cell heights (first cell height and second cell height) within the same row framework. Extension regions provide the flexibility to adapt to different cell sizes without requiring separate row designs. This multi-functional cell row can host both low threshold voltage and high threshold voltage cells, enabling optimized circuit design without increasing overall system complexity
Solution Approach 2:
The invention introduces vertical dimensionality variation by allowing cells of different heights within the same row, rather than being constrained to a single height plane. This dimensional flexibility enables the cell library to include diverse cell sizes for different functions while the place and route tool manages the vertical arrangement through extension regions, resolving the contradiction between design simplicity and circuit optimization capability
Data Source
AI summary
A system and method for designing integrated circuits is disclosed. An embodiment comprises placing a standard cell with a first cell height into a cell row with a different height. The standard cell may have a height smaller than the cell row or else may have a height that is larger than the cell row. Vertical fillers and horizontal fillers are utilized to extend and connect the standard cell to adjacent cells without having to redesign the entire cell row.