Variable-Height Interconnect Structure for Semiconductor RC Control
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Solution Overview
Problem
The formation of interconnect structures in semiconductor devices with high device density and performance requires improved resistance and capacitance (RC) characteristics, which is challenging due to the complexity of forming metal lines and vias with varying heights and distances.
Innovation Solution
The semiconductor device incorporates an interconnect structure with metal lines and vias of different heights, where resistance-dominant portions have a greater height and capacitance-dominant portions have a smaller height, achieved through precise patterning and layer formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal lines with varying heights are formed to improve RC characteristics, then resistance and capacitance performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies local quality by forming metal lines with different heights at different locations based on their specific functional requirements. Resistance-dominant portions (such as power rails and word lines) are formed with greater height to reduce resistance, while capacitance-dominant portions (such as bit lines) are formed with smaller height to reduce capacitance. This localized differentiation optimizes RC characteristics for each interconnect type without requiring complete restructuring of the entire interconnect system.
Solution Approach 2:
The patent segments the interconnect formation process into multiple patterning steps, including first and second patterning operations that create different metal line heights. The process divides the metal structure formation into discrete stages where different regions are patterned and etched to achieve the desired height variations. This segmentation allows precise control over the three-dimensional configuration of metal lines while maintaining manufacturing feasibility.
2Quantity of substance
If metal-to-metal distance is reduced to increase device density, then device density is improved, but RC characteristics deteriorate
Solution Approach 1:
The patent transitions from two-dimensional planar interconnect design to three-dimensional vertical structuring by forming metal lines with different heights. This dimensional change allows metal lines to be stacked and arranged in multiple layers, effectively increasing device density without proportionally decreasing the horizontal metal-to-metal distance. The vertical dimension provides additional space for routing and reduces parasitic effects while maintaining acceptable spacing between adjacent interconnects.
Data Source
AI summary
Provided is a semiconductor device which includes: a base layer including at least one transistor structure; and an interconnect structure above the base layer in a 3rd direction, wherein the interconnect structure includes a 1st metal line, a 2nd metal line, and at least one another metal line extended in a 1st direction and arranged at a 2nd direction, wherein at least a 1st portion of the 1st metal line having a 1st metal-to-metal distance to at least a portion of another metal line adjacent thereto in the 2nd direction has a greater height than at least a 1st portion of the 2nd metal line having a 2nd metal-to-metal distance to at least a portion of another metal line adjacent thereto in the 2nd direction, wherein the 1st metal-to-metal distance is greater than the 2nd metal-to-metal distance, and wherein the 1st direction and the 2nd direction horizontally intersect each other, and vertically intersect the 3rd direction.