Variable High Voltage Word Line Driver Circuit for Memory Devices
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Solution Overview
Problem
The reliability of word line driver circuits in memory devices is compromised due to gate stress on transistors caused by high voltages, leading to decreased performance and reliability over time.
Innovation Solution
A memory device with a word line driver circuit that generates a lower high voltage based on a command, allowing for different voltage levels to be applied to various word lines, reducing gate stress by using a variable high voltage line to drive word lines to ground, high, or lower high voltage levels depending on their selection status.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a high voltage greater than a power supply voltage is applied to drive the word line to turn on the NMOS cell transistor, then the memory device can operate in high capacity mode, but gate stress is applied to the transistor causing decreased reliability
Solution Approach 1:
The patent applies dynamics by making the high voltage level variable rather than fixed. The word line driver circuit selectively applies different high voltage levels (first high voltage or second high voltage) based on operational modes. This dynamic voltage adjustment allows the system to optimize between performance and reliability by using appropriate voltage levels for different operating conditions, thereby reducing gate stress while maintaining memory functionality.
Solution Approach 2:
The patent changes the voltage parameter from a single fixed high voltage to multiple variable high voltage levels. The voltage generator circuit produces at least two different high voltage levels, and the word line driver circuit selectively applies these different voltage levels based on the operational mode. This parameter change enables the system to reduce gate stress on transistors by using lower high voltage levels when full performance is not required, thus improving reliability while maintaining operational capability.
2Reliability
If the transistor characteristics are changed by gate stress, then the word line driver circuit reliability decreases, but maintaining high voltage application is necessary for memory operation
Solution Approach 1:
The patent changes the voltage parameter from a single fixed high voltage to multiple variable high voltage levels. The voltage generator circuit produces at least two different high voltage levels, and the word line driver circuit selectively applies these different voltage levels based on the operational mode. This parameter change enables the system to reduce gate stress on transistors by using lower high voltage levels when full performance is not required, thus improving reliability while maintaining operational capability.
Solution Approach 2:
The patent applies dynamics by making the high voltage level variable rather than fixed. The word line driver circuit selectively applies different high voltage levels (first high voltage or second high voltage) based on operational modes. This dynamic voltage adjustment allows the system to optimize between performance and reliability by using appropriate voltage levels for different operating conditions, thereby reducing gate stress while maintaining memory functionality.
Data Source
AI summary
A memory device includes a word line driver circuit, which can advantageously reduce gate stress on a transistor using a lower high voltage that varies with a command, and an operating method of the memory device. The memory device includes a plurality of memory blocks, provides a high voltage or the lower high voltage to a variable high voltage line in response to a block select signal, and changes a level of the lower high voltage to a low voltage level, a medium voltage level, or a high voltage level based on the command. The memory device applies the lower high voltage to gates of P-type metal oxide semiconductor (PMOS) transistors connected to a word line driving signal, which drives word lines of non-selected memory blocks among the plurality of memory blocks.