Variable In-Plane Signal Ground Reference Configurations

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Solution Overview

Problem

High-performance electronic packages face a challenge in balancing signal integrity for both cross-talk and loss-dominated interfaces, as standard designs must choose between higher differential IO insertion loss or higher single-ended IO cross-talk, leading to suboptimal performance and increased cost or Z-height.

Innovation Solution

The implementation of a variable in-plane signal to ground reference scheme allows for independent tuning of impedance for differential pairs, decoupling it from substrate dielectric thickness, enabling flexible routing that minimizes cross-talk and loss by varying the spacing between differential signaling traces and ground planes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the dielectric thickness is increased to reduce cross-talk for single-ended interfaces, then single-ended signal integrity is improved, but differential signal loss increases due to wider required trace widths

Engineering Contradiction:
Improvesingle-ended signal integrityVSAvoiddifferential signal loss
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies local quality by implementing different dielectric thicknesses at different locations within the package. Specifically, thinner dielectric layers are used in regions where single-ended signals are routed to minimize cross-talk, while thicker dielectric layers are used in regions where differential signals are routed to allow for wider trace widths and reduce signal loss. This spatial variation in dielectric thickness allows each signal type to be optimized for its specific requirements without compromising the other.

Inventive Principle:
Principle #3Local quality

2Reliability

If the dielectric thickness is decreased to reduce differential signal loss, then differential signal integrity is improved, but single-ended cross-talk increases

Engineering Contradiction:
Improvedifferential signal integrityVSAvoidsingle-ended cross-talk
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent implements local quality by creating zones with different dielectric thicknesses optimized for specific signal types. Thinner dielectric regions are positioned adjacent to single-ended signal traces to reduce cross-talk, while thicker dielectric regions are positioned for differential signal pairs to enable wider trace widths and reduce insertion loss. This localized optimization resolves the contradiction by allowing each signal type to operate in its optimally configured environment.

Inventive Principle:
Principle #3Local quality

3Reliability

If skip layer routing is used for differential signals to reduce loss, then differential signal integrity is improved, but package layer count and Z-height increase

Engineering Contradiction:
Improvedifferential signal integrityVSAvoidpackage layer count
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies parameter changes by modifying the dielectric thickness parameter in the vertical dimension rather than adding more horizontal layers. By varying the dielectric thickness locally, the patent achieves the signal integrity benefits of skip layer routing (thicker effective dielectric for differential signals) without actually skipping layers or increasing the package layer count. This resolves the contradiction by achieving the same electrical performance through a different physical parameter adjustment.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11705390B2Variable in-plane signal to ground reference configurations
Publication Date: 2023.07.18 INTEL CORP
  • US11705390B2 patent drawing
  • US11705390B2 patent drawing
  • US11705390B2 patent drawing

AI summary

Embodiments disclosed herein include electronic packages with improved differential signaling architectures. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises alternating metal layers and dielectric layers. In an embodiment, a first trace is embedded in the package substrate, where the first trace has a first thickness that extends from a first metal layer to a second metal layer. In an embodiment, the electronic package further comprises a first ground plane laterally adjacent to a first side of the first trace, and a second ground plane laterally adjacent to a second side of the first trace.