Variable Instruction Word Length for VLIW Memory Efficiency
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Solution Overview
Problem
Existing VLIW processors face inefficiencies in memory usage due to the need for 'no-operation' instructions when not all functional units can be supplied with operations, leading to excessive memory overhead and reduced parallelism.
Innovation Solution
The processor dynamically adjusts the length and width of instruction words based on the address range, using multiple memory units with varying widths and clock gating to optimize memory usage and functional unit selection, allowing for high parallelism in inner loops and efficient storage outside them.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a fixed number of instructions are fetched in each instruction cycle, then the processor can execute operations in parallel, but memory usage becomes excessive when not all functional units can be supplied with operations
Solution Approach 1:
The patent applies dynamics by making the instruction word length variable rather than fixed. The processor dynamically adjusts the number of instructions fetched based on the address range: longer instruction words for inner loops (high parallelism needed) and shorter instruction words for outer loops (memory efficiency prioritized). This dynamic adaptation resolves the contradiction between maintaining high productivity and reducing memory usage.
Solution Approach 2:
The patent changes the parameter of instruction word length based on address range detection. By detecting whether the current instruction is from an inner loop or outer loop, the system modifies the instruction word length parameter accordingly. This parameter change allows the system to optimize both parallelism and memory efficiency in different program sections.
2Ease of operation
If no-operation instructions are included for functional units without operations, then all functional units can be supplied with instructions, but memory overhead increases
Solution Approach 1:
The patent applies partial action by fetching only the necessary number of instructions for the current functional units. Instead of always fetching a fixed number of instructions (including unnecessary no-operation instructions), the system fetches only the required number based on address range, thereby avoiding memory overhead while still ensuring all active functional units receive their operations.
3Quantity of substance
If instruction word length is reduced to save memory, then storage efficiency improves, but the maximum level of parallelism is reduced
Solution Approach 1:
The system dynamically adjusts instruction word length based on the program section being executed. In inner loops where high parallelism is needed, longer instruction words are used. In outer loops where memory efficiency is prioritized, shorter instruction words are used. This dynamic behavior allows the system to achieve both high storage efficiency and high parallelism in different contexts.
Data Source
AI summary
A data processing apparatus has an instruction memory system arranged to output an instruction word addressed by an instruction address. An instruction execution unit, processes a plurality of instructions from the instruction word in parallel. A detection unit, detects in which of a plurality of ranges the instruction address lies. The detection unit is coupled to the instruction execution unit and/or the instruction memory system, to control a way in which the instruction execution unit parallelizes processing of the instructions from the instruction word, dependent on a detected range. In an embodiment the instruction execution unit and/or the instruction memory system adjusts a width of the instruction word that determines a number of instructions from the instruction word that is processed in parallel, dependent on the detected range.