Variable Latency Execution Pipeline Optimization
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Solution Overview
Problem
Existing processor pipelines face performance issues due to variable latency instructions, which can lead to instruction stalls and reduced throughput.
Innovation Solution
The implementation of a dispatch unit that dispatches instructions to issue queues, which feed into execution pipelines with separate execution engines for variable and fixed latency instructions. When a variable latency instruction completes, a request is issued to the instruction queue control logic, allowing for a stall in the pipeline to accommodate the result, thereby providing a bypass and reducing execution time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If variable latency instructions are executed in a standard pipeline, then instruction diversity is supported, but pipeline stalls occur and throughput decreases
Solution Approach 1:
The execution pipeline is segmented into separate execution engines: a first execution engine dedicated to variable latency instructions and a second execution engine dedicated to fixed latency instructions. This segmentation allows each engine to be optimized for its specific instruction type, preventing variable latency instructions from causing stalls in the fixed latency pipeline and thereby maintaining high throughput while supporting instruction diversity
Solution Approach 2:
A completion queue is introduced as an intermediary structure between the execution engines and the register file. The completion queue buffers results from variable latency instructions and manages their delivery to subsequent instructions, allowing the pipeline to continue executing instructions without waiting for variable latency operations to complete, thus eliminating stalls while maintaining correctness
2Adaptability or versatility
If variable latency instructions are executed, then complex operations are supported, but execution time varies and stalls increase
Solution Approach 1:
The system performs preliminary actions by pre-allocating a dedicated first execution engine for variable latency instructions and establishing a completion queue structure in advance. This preparation allows variable latency instructions to be executed without impacting fixed latency instruction flow, reducing the time loss associated with pipeline stalls while maintaining support for complex operations
Solution Approach 2:
The completion queue dynamically manages the delivery of results from variable latency instructions to subsequent instructions. It adapts to the varying execution times by buffering results and delivering them when dependencies are satisfied, allowing the pipeline to maintain high utilization without stalls despite the dynamic execution times of variable latency operations
Data Source
AI summary
Disclosed embodiments provide techniques for instruction execution in computer processors. A dispatch unit dispatches instructions to one or more issue queues. Instructions from the issue queues feed into execution pipelines. Each execution pipeline includes instruction queue control logic, and two execution engines. A first execution engine is assigned to variable latency instructions while a second execution engine is assigned to fixed latency instructions. While a variable latency instruction executes, fixed latency instructions can be issued, executed, and completed. When the variable latency instruction finishes execution, a request is issued by the first execution engine to the instruction queue control logic. In response, the instruction queue control logic introduces a stall in a common write-back pipeline, allowing the variable latency instruction to complete. The result of the variable latency instruction is provided to a depending fixed latency instruction via a bypass path.